Memory controller implemented.
This commit is contained in:
Anachronaut
@@ -0,0 +1,40 @@
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; Running off the end of a bank.
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;
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; Bank 2 is the bank table: 256 banks at eight bytes each, so 2048 bytes exactly. The
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; last byte is at 0x07FF and there is nothing at 0x0800. A bank knowing how big it is
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; means the difference shows up as a fault at the instruction that overran, instead of
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; quietly reading whatever happened to be next in the emulator's memory.
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;
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; Nothing is installed for BankFault here, so the machine stops.
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;
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; Correct output is:
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; O the last byte of the bank was read without complaint
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; a fault naming port 233, which is the controller's Data port, and a non zero exit.
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#Program
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start:
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INIA 0d2
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OUTA 0xE0 ; SourceBank = 2
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INIA 0x07
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OUTA 0xE1
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INIA 0xFF
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OUTA 0xE2 ; 0x07FF, the last byte there is
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INA 0xE9 ; Fine.
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INIA 0d79 ; 'O'
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OUTA 0x00
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INIA 0x0A
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OUTA 0x00
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INIA 0x08
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OUTA 0xE1
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RSTA
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OUTA 0xE2 ; 0x0800, one past the end
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INA 0xE9 ; Refused: BankFault.
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; Never reached.
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INIA 0d88 ; 'X'
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OUTA 0x00
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HALT
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@@ -0,0 +1,210 @@
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; Blits and fills.
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;
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; A blit moves a run of bytes between any two banks, including from one place in a bank
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; to another. A fill writes one byte across a run. Both are instantaneous: waiting
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; belongs to a peripheral that has something to wait for, not to the moving of bytes.
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;
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; Everything a transfer will touch is checked before any of it moves, so a transfer that
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; would run out of bank refuses outright rather than stopping halfway and leaving memory
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; in a state nobody asked for. The last case here proves that: the blit is refused, and
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; the bytes it would have written are still what they were.
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;
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; Correct output is:
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; blitted copied from one place in Data Memory to another
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; .... filled with a byte of our choosing
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; DE AD blitted from Data Memory into Program Memory
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; untouched a refused blit moved nothing at all
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; ABABCDEFGH an overlapping blit slid the bytes rather than repeating one
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#Include print.asm
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#Program
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start:
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; ---- A blit inside Data Memory, which is what a memcpy is here. ----
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SETD.0 Message
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CALL aimSource
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SETD.0 Landing
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CALL aimDest
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INIA 0d8
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CALL setLength ; "blitted" and its terminator.
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INIA 0x01
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OUTA 0xE8 ; Blit.
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SETD.0 Landing
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CALL printString
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CALL lineFeed
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; ---- A fill, with a byte of our choosing rather than only zero. ----
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SETD.0 Landing
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CALL aimDest
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INIA 0x2E ; '.', into SourceLow, which is where a fill takes its byte.
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OUTA 0xE2
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INIA 0d4
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CALL setLength
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INIA 0x02
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OUTA 0xE8 ; Fill.
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; Terminate it so printString knows where to stop.
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SETD.0 Landing
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DPUP.0 0d04
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RSTA
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STA.0
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SETD.0 Landing
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CALL printString
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CALL lineFeed
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; ---- Data Memory into Program Memory. This is what a loader does. ----
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SETD.0 Code
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CALL aimSource
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SETD.0 Target
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CALL aimDestProgram
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INIA 0d2
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CALL setLength
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INIA 0x01
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OUTA 0xE8 ; Blit.
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; Read it back out of Program Memory to prove it landed.
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SETD.0 Target
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CALL aimSourceProgram
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CALL readAndPrint
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CALL readAndPrint
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CALL lineFeed
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; ---- A blit that would run past the end of bank 2. ----
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; Bank 2 is 2048 bytes. Starting at 2040 and asking for 16 does not fit, so the whole
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; thing is refused and Landing keeps what it already had.
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SETD.0 Untouched
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CALL aimSource
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SETD.0 Landing
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CALL aimDest
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INIA 0d10
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CALL setLength
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INIA 0x01
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OUTA 0xE8 ; This one works, so Landing says "untouched".
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INIA 0d2
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OUTA 0xE0 ; SourceBank = 2, the bank table.
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INIA 0x07
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OUTA 0xE1
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INIA 0xF8
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OUTA 0xE2 ; 0x07F8, eight bytes from the end.
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SETD.0 Landing
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CALL aimDest
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INIA 0d16
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CALL setLength
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INIA 0x01
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OUTA 0xE8 ; Refused: it would read past the end of bank 2.
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SETD.0 Landing
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CALL printString
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CALL lineFeed
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; ---- A blit whose source and destination overlap. ----
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; Sliding a run of bytes along inside its own bank is an ordinary thing to want, so it
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; works rather than quietly repeating the first byte the way a naive forward copy does.
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SETD.0 Slide
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CALL aimSource
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SETD.0 Slide
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DPUP.0 0d02
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CALL aimDest
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INIA 0d8
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CALL setLength
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INIA 0x01
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OUTA 0xE8
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SETD.0 Slide
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CALL printString
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CALL lineFeed
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HALT
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; ---- Helpers. DP0 holds the address to aim at. ----
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aimSource:
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INIA 0d1 ; Bank 1, Data Memory.
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OUTA 0xE0
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BRI aimSourceAddress
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aimSourceProgram:
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RSTA ; Bank 0, Program Memory.
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OUTA 0xE0
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aimSourceAddress:
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PSHD.0
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POPA
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POPB
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OUTB 0xE1
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OUTA 0xE2
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RET
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aimDest:
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INIA 0d1 ; Bank 1, Data Memory.
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OUTA 0xE3
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BRI aimDestAddress
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aimDestProgram:
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RSTA ; Bank 0, Program Memory.
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OUTA 0xE3
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aimDestAddress:
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PSHD.0
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POPA
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POPB
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OUTB 0xE4
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OUTA 0xE5
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RET
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; A is the length, which is never more than a byte in this program.
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setLength:
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PSHA
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RSTA
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OUTA 0xE6
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POPA
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OUTA 0xE7
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RET
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readAndPrint:
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INA 0xE9
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CALL printByteHex
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CALL blankSpace
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RET
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; The refused blit is caught so the program can carry on and show that nothing moved.
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; The command write is two bytes, an opcode and a port, so stepping by two gets past it.
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refusedHandler:
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MVSD.0
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DPUP.0 0d14
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LDA.0
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CCF
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INIB 0d2
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ADD
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MVQA
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STA.0
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BRC refusedCarried
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RETI
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refusedCarried:
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DPDN.0 0d01
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LDA.0
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INCA
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STA.0
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RETI
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; Never executed, only written over.
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Target:
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0x00 0x00
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#Data
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Message:
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"blitted"
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Untouched:
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"untouched"
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Code:
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0xDE 0xAD
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Landing:
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#Reserve 0d16
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Slide:
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"ABCDEFGH"
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#Reserve 0d4
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#Vectors
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BankFault refusedHandler
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@@ -0,0 +1,66 @@
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; Reads Program Memory through the memory controller.
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;
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; Nothing on SplitBit could do this before. The CPU cannot reach its own code, which is
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; what a Harvard machine is, and this is the device that can.
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;
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; The bytes read back are a marker written into the Program Segment after the HALT, where
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; nothing executes them. The controller is aimed at it using the label's own address, so
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; this checks the controller against what the source says rather than against a guess
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; about where the assembler put things.
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;
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; The address steps on by itself, so reading a run of bytes is a loop over one
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; instruction rather than four.
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;
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; Correct output is:
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; DE AD BE EF the marker, read out of Program Memory
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; 01 FF bank 0's record in bank 2: present, owned by the machine
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; 00 00 and its capacity, where zero means the whole 64K
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#Include print.asm
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#Program
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start:
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; Aim the controller at the marker, using the marker's own address.
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SETD.0 Marker
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PSHD.0 ; High byte, then low, so the low byte comes off first.
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POPA
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POPB
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PSHA ; Keep the low byte while A is needed for something else.
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RSTA
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OUTA 0xE0 ; SourceBank = 0, which is Program Memory.
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OUTB 0xE1 ; SourceHigh
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POPA
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OUTA 0xE2 ; SourceLow
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CALL readAndPrint
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CALL readAndPrint
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CALL readAndPrint
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CALL readAndPrint
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CALL lineFeed
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; Now the bank table, which is bank 2. Bank 0's record comes first.
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INIA 0d2
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OUTA 0xE0
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RSTA
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OUTA 0xE1
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OUTA 0xE2
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CALL readAndPrint ; Flags: present.
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CALL readAndPrint ; Owner: the machine itself.
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CALL lineFeed
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CALL readAndPrint ; Capacity, high byte.
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CALL readAndPrint ; Capacity, low byte.
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CALL lineFeed
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HALT
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readAndPrint:
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INA 0xE9
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CALL printByteHex
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CALL blankSpace
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RET
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; Never executed. It is here to be read rather than run.
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Marker:
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0xDE 0xAD 0xBE 0xEF
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@@ -0,0 +1,127 @@
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; Writes Program Memory through the controller, and gets turned away from what it may
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; not touch.
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;
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; Writing code is the thing SplitBit's instruction set deliberately cannot do. The
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; controller can, which is what makes a loader possible. The marker below is written and
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; then read back through the controller, so the change is observed rather than assumed.
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;
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; The two refusals are the other half. Bank 2 is the bank table and is read only, so
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; writing to it is a GuardViolation. Bank 200 has nothing registered in it, so naming it
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; is a BankFault. Both handlers step the saved address past the instruction that was
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; refused, the way any handler carrying on past a fault has to.
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;
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; Correct output is:
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; AA BB the marker after being written through the controller
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; readonly
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; nobank
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; done
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#Include print.asm
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#Program
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start:
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; Aim both ends of the controller at the marker.
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SETD.0 Marker
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PSHD.0
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POPA
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POPB
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PSHA
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PSHB
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RSTA
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OUTA 0xE0 ; SourceBank = 0
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OUTA 0xE3 ; DestBank = 0
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POPB
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OUTB 0xE1 ; SourceHigh
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OUTB 0xE4 ; DestHigh
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POPA
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OUTA 0xE2 ; SourceLow
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OUTA 0xE5 ; DestLow
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; Write two bytes over the marker. This is Program Memory being changed at run time.
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INIA 0xAA
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OUTA 0xE9
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INIA 0xBB
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OUTA 0xE9
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; Read them back the same way, to prove they landed.
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CALL readAndPrint
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CALL readAndPrint
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CALL lineFeed
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; Bank 2 is the bank table, and it is read only.
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INIA 0d2
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OUTA 0xE3
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RSTA
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OUTA 0xE4
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OUTA 0xE5
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INIA 0d1
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OUTA 0xE9 ; Refused: GuardViolation.
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; Bank 200 has nothing in it.
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INIA 0d200
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OUTA 0xE3
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INIA 0d1
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OUTA 0xE9 ; Refused: BankFault.
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SETD.0 Done
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CALL printString
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CALL lineFeed
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HALT
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readAndPrint:
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INA 0xE9
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CALL printByteHex
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CALL blankSpace
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RET
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readOnlyHandler:
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SETD.0 ReadOnly
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CALL printString
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CALL lineFeed
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BRI stepPastRefusal
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noBankHandler:
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SETD.0 NoBank
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CALL printString
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CALL lineFeed
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BRI stepPastRefusal
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; Steps the saved address past the refused instruction. OUT is two bytes, an opcode and
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; a port, so two is what it takes.
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stepPastRefusal:
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MVSD.0
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DPUP.0 0d14
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LDA.0
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CCF
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INIB 0d2
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ADD
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MVQA
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STA.0
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BRC carried
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RETI
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carried:
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DPDN.0 0d01
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LDA.0
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INCA
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STA.0
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RETI
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; Never executed.
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Marker:
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0x00 0x00
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#Data
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ReadOnly:
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"readonly"
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NoBank:
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"nobank"
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Done:
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"done"
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#Vectors
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GuardViolation readOnlyHandler
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BankFault noBankHandler
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@@ -0,0 +1,172 @@
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; The fence.
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;
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; A guarded range is a fence rather than a wall. Any program may raise one and any
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; program may lower it, so nobody is ever told no. What it stops is walking into
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; something by accident, which is the failure that costs an afternoon: without it, code
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; that gets walked over is found much later, when the wreckage is finally executed and
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; the evidence is long gone.
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;
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; The handler reads the controller's destination registers to say where the refused write
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; was aimed. That is the whole point of catching it at the instruction that did it: the
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; address is still sitting there to be read.
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;
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; The addresses here are absolute rather than labels, so that this says the same thing no
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; matter what else ends up in the Data Segment. Data Memory is 64K and this program uses
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; a hundred bytes of it, so 0x0200 is empty ground.
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;
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; Correct output is:
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; outside ok a write just below the fence went through
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; caught 0200 a write inside it was refused, and the handler says where
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; caught 01FC a blit that merely clipped it was refused whole
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; read ok reading inside the fence is allowed: it guards writing
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; lowered ok after GuardOff the same write goes through
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; fenced 05 the bank table shows bank 1 present and fenced
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#Include print.asm
|
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#Program
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start:
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; Fence off 0x0200 to 0x020F in Data Memory.
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INIA 0d1
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OUTA 0xEB ; GuardBank = 1
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INIA 0x02
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OUTA 0xEC
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RSTA
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OUTA 0xED ; GuardStart = 0x0200
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INIA 0x02
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OUTA 0xEE
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INIA 0x0F
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OUTA 0xEF ; GuardEnd = 0x020F
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INIA 0x10
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OUTA 0xE8 ; GuardOn
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; Just below the fence is ordinary ground.
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INIA 0x01
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OUTA 0xE4
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INIA 0xFF
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OUTA 0xE5 ; Dest = 0x01FF
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INIA 0d1
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OUTA 0xE3 ; DestBank = 1
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INIA 0x41
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OUTA 0xE9
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SETD.0 OutsideOk
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CALL say
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; Inside it is not.
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INIA 0x02
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OUTA 0xE4
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RSTA
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OUTA 0xE5 ; Dest = 0x0200
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INIA 0x42
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OUTA 0xE9 ; Refused.
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; A blit from 0x01FC for eight bytes runs to 0x0203, so it clips the fence. It is
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; refused whole rather than doing the four bytes that would have fitted.
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INIA 0x01
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OUTA 0xE4
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INIA 0xFC
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OUTA 0xE5 ; Dest = 0x01FC
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INIA 0d1
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OUTA 0xE0
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RSTA
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OUTA 0xE1
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OUTA 0xE2 ; Source = bank 1, 0x0000
|
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OUTA 0xE6
|
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INIA 0d8
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OUTA 0xE7 ; Length = 8
|
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INIA 0x01
|
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OUTA 0xE8 ; Refused.
|
||||
|
||||
; Reading inside a fence is allowed. A debugger has to be able to see what is being
|
||||
; protected.
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INIA 0d1
|
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OUTA 0xE0
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||||
INIA 0x02
|
||||
OUTA 0xE1
|
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RSTA
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OUTA 0xE2 ; Source = 0x0200
|
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INA 0xE9
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SETD.0 ReadOk
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CALL say
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|
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; Lower it, and the write that was refused goes through.
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||||
INIA 0x11
|
||||
OUTA 0xE8 ; GuardOff
|
||||
INIA 0x02
|
||||
OUTA 0xE4
|
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RSTA
|
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OUTA 0xE5
|
||||
INIA 0x43
|
||||
OUTA 0xE9
|
||||
SETD.0 LoweredOk
|
||||
CALL say
|
||||
|
||||
; Raise it again, and read the flags back out of the bank table, where a fence is
|
||||
; published along with everything else about a bank.
|
||||
INIA 0x10
|
||||
OUTA 0xE8
|
||||
INIA 0d2
|
||||
OUTA 0xE0
|
||||
RSTA
|
||||
OUTA 0xE1
|
||||
INIA 0d8
|
||||
OUTA 0xE2 ; Bank 1's record begins at 8.
|
||||
SETD.0 Fenced
|
||||
CALL printString
|
||||
CALL blankSpace
|
||||
INA 0xE9
|
||||
CALL printByteHex
|
||||
CALL lineFeed
|
||||
HALT
|
||||
|
||||
; Says where the refused write was aimed, by reading the controller's own registers.
|
||||
guardHandler:
|
||||
SETD.0 Caught
|
||||
CALL printString
|
||||
CALL blankSpace
|
||||
INA 0xE4 ; DestHigh
|
||||
CALL printByteHex
|
||||
INA 0xE5 ; DestLow
|
||||
CALL printByteHex
|
||||
CALL lineFeed
|
||||
|
||||
; Step past the refused instruction. Every write here is an opcode and a port.
|
||||
MVSD.0
|
||||
DPUP.0 0d14
|
||||
LDA.0
|
||||
CCF
|
||||
INIB 0d2
|
||||
ADD
|
||||
MVQA
|
||||
STA.0
|
||||
BRC stepCarried
|
||||
RETI
|
||||
stepCarried:
|
||||
DPDN.0 0d01
|
||||
LDA.0
|
||||
INCA
|
||||
STA.0
|
||||
RETI
|
||||
|
||||
say:
|
||||
CALL printString
|
||||
CALL lineFeed
|
||||
RET
|
||||
|
||||
#Data
|
||||
|
||||
OutsideOk:
|
||||
"outside ok"
|
||||
Caught:
|
||||
"caught"
|
||||
ReadOk:
|
||||
"read ok"
|
||||
LoweredOk:
|
||||
"lowered ok"
|
||||
Fenced:
|
||||
"fenced"
|
||||
|
||||
#Vectors
|
||||
|
||||
GuardViolation guardHandler
|
||||
@@ -0,0 +1,125 @@
|
||||
; A program that loads a program.
|
||||
;
|
||||
; This is what the memory controller was built for. The bytes of a small routine sit in
|
||||
; the Data Segment the way a program read off a disk would. The loader blits them into
|
||||
; Program Memory, writes their address into a software vector, and calls it. Nothing
|
||||
; about that routine was known to the assembler as code: to the loader it is data, and it
|
||||
; becomes code only because it was put somewhere the CPU fetches from.
|
||||
;
|
||||
; Installing the vector at run time is the part worth watching. The argument that started
|
||||
; the whole controller design was that a vector table nothing can write is not really a
|
||||
; vector table. Vector 20 is empty when this program starts and holds a real handler by
|
||||
; the time it is called, and nothing but the controller could have put it there.
|
||||
;
|
||||
; WHAT THIS DOES NOT SOLVE:
|
||||
;
|
||||
; The payload works at whatever address it lands at only because it contains no
|
||||
; addresses. It is INIA and OUTA and a RETI, and none of those name a place. The moment a
|
||||
; loaded routine contains a branch, a CALL, or a SETD, it holds an address that was fixed
|
||||
; when it was assembled, and it will be wrong everywhere except where it was assembled
|
||||
; for. SplitBit has no answer to that yet. Loading works; relocating does not exist.
|
||||
;
|
||||
; Correct output is:
|
||||
; before the vector is still empty here
|
||||
; loaded printed by code that was data a moment ago
|
||||
; back and RETI came home
|
||||
|
||||
#Include print.asm
|
||||
|
||||
#Program
|
||||
|
||||
start:
|
||||
SETD.0 Before
|
||||
CALL say
|
||||
|
||||
; ---- Put the payload into Program Memory. ----
|
||||
SETD.0 Payload
|
||||
CALL aimSourceData
|
||||
SETD.0 LandingZone
|
||||
CALL aimDestProgram
|
||||
INIA 0d29
|
||||
CALL setLength
|
||||
INIA 0x01
|
||||
OUTA 0xE8 ; Blit: Data Memory into Program Memory.
|
||||
|
||||
; ---- Write its address into software vector 20. ----
|
||||
; The table is at 0xFC00 and entries are two bytes, so vector 20 is at 0xFC28.
|
||||
RSTA
|
||||
OUTA 0xE3 ; DestBank = 0, Program Memory.
|
||||
INIA 0xFC
|
||||
OUTA 0xE4
|
||||
INIA 0x28
|
||||
OUTA 0xE5
|
||||
SETD.0 LandingZone
|
||||
PSHD.0
|
||||
POPA
|
||||
POPB
|
||||
OUTB 0xE9 ; High byte of the handler's address.
|
||||
OUTA 0xE9 ; Low byte. The Data port steps on by itself.
|
||||
|
||||
; ---- Call it. ----
|
||||
SWI 0d20
|
||||
|
||||
SETD.0 Back
|
||||
CALL say
|
||||
HALT
|
||||
|
||||
; DP0 holds the address to aim at.
|
||||
aimSourceData:
|
||||
INIA 0d1
|
||||
OUTA 0xE0
|
||||
PSHD.0
|
||||
POPA
|
||||
POPB
|
||||
OUTB 0xE1
|
||||
OUTA 0xE2
|
||||
RET
|
||||
|
||||
aimDestProgram:
|
||||
RSTA
|
||||
OUTA 0xE3
|
||||
PSHD.0
|
||||
POPA
|
||||
POPB
|
||||
OUTB 0xE4
|
||||
OUTA 0xE5
|
||||
RET
|
||||
|
||||
setLength:
|
||||
PSHA
|
||||
RSTA
|
||||
OUTA 0xE6
|
||||
POPA
|
||||
OUTA 0xE7
|
||||
RET
|
||||
|
||||
say:
|
||||
CALL printString
|
||||
CALL lineFeed
|
||||
RET
|
||||
|
||||
; Where the payload lands. Reserving it means the assembler knows the room is spoken for,
|
||||
; so nothing else is ever placed here.
|
||||
LandingZone:
|
||||
#Reserve 0d48
|
||||
|
||||
#Data
|
||||
|
||||
Before:
|
||||
"before"
|
||||
Back:
|
||||
"back"
|
||||
|
||||
; The payload, as bytes rather than as code. It prints "loaded" and returns. Written out
|
||||
; by hand because SplitBit has no linker: to this program it is just so much data.
|
||||
;
|
||||
; INIA 'l' OUTA 0 INIA 'o' OUTA 0 ... and so on, then RETI
|
||||
Payload:
|
||||
0x26 0x6C 0xD1 0x00
|
||||
0x26 0x6F 0xD1 0x00
|
||||
0x26 0x61 0xD1 0x00
|
||||
0x26 0x64 0xD1 0x00
|
||||
0x26 0x65 0xD1 0x00
|
||||
0x26 0x64 0xD1 0x00
|
||||
0x26 0x0A 0xD1 0x00
|
||||
0x19
|
||||
@@ -0,0 +1,25 @@
|
||||
; A device refuses, and nothing is installed to deal with it.
|
||||
;
|
||||
; The machine has to stop where it stands and say which port refused and where. Letting
|
||||
; execution carry on would mean the program continues as though the access had worked,
|
||||
; which is the failure the fault trap exists to prevent.
|
||||
;
|
||||
; Correct output is:
|
||||
; O
|
||||
; a fault naming port 17, and a non zero exit.
|
||||
|
||||
#Program
|
||||
|
||||
start:
|
||||
INIA 0d79 ; 'O', so it is clear how far it got.
|
||||
OUTA 0x00
|
||||
INIA 0x0A
|
||||
OUTA 0x00
|
||||
|
||||
INIA 0d1
|
||||
OUTA 0x11 ; The device refuses, and no handler is installed.
|
||||
|
||||
; Never reached.
|
||||
INIA 0d88 ; 'X'
|
||||
OUTA 0x00
|
||||
HALT
|
||||
@@ -0,0 +1,74 @@
|
||||
; Tests a device refusing what it was asked to do.
|
||||
;
|
||||
; Interrupting is a device asking for attention later. Refusing is a device saying no to
|
||||
; the instruction happening now, so it has to stop the machine where it stands instead of
|
||||
; letting execution carry on past the mistake.
|
||||
;
|
||||
; The device on port 0x11 refuses everything, in both directions, so that this path can
|
||||
; be exercised without the memory controller. A refusal names a software vector, so the
|
||||
; handler knows what happened from the entry it arrived through.
|
||||
;
|
||||
; The handler steps the saved address past the instruction that was refused, the same way
|
||||
; the fault handler steps past a byte that would not decode. Without that a bare RETI
|
||||
; would meet the same refused instruction again forever.
|
||||
;
|
||||
; Correct output is:
|
||||
; caught the handler caught a refused write
|
||||
; caught and a refused read
|
||||
; done
|
||||
|
||||
#Include print.asm
|
||||
|
||||
#Program
|
||||
|
||||
start:
|
||||
INIA 0d1
|
||||
OUTA 0x11 ; Refused. The handler runs and steps us past this.
|
||||
|
||||
INA 0x11 ; Refused as well, and reads are caught the same way.
|
||||
|
||||
SETD.0 Done
|
||||
CALL printString
|
||||
CALL lineFeed
|
||||
HALT
|
||||
|
||||
; A refusal arrives with a full frame, so the handler may use whatever it likes.
|
||||
refusalHandler:
|
||||
CALL reportRefusal
|
||||
|
||||
; Step the saved address past the instruction that was refused. Both OUT and IN are
|
||||
; two bytes, an opcode and a port, so two is what it takes.
|
||||
MVSD.0
|
||||
DPUP.0 0d14
|
||||
LDA.0
|
||||
CCF
|
||||
INIB 0d2
|
||||
ADD
|
||||
MVQA
|
||||
STA.0
|
||||
BRC carried
|
||||
RETI
|
||||
|
||||
carried:
|
||||
DPDN.0 0d01
|
||||
LDA.0
|
||||
INCA
|
||||
STA.0
|
||||
RETI
|
||||
|
||||
reportRefusal:
|
||||
SETD.0 Caught
|
||||
CALL printString
|
||||
CALL lineFeed
|
||||
RET
|
||||
|
||||
#Data
|
||||
|
||||
Caught:
|
||||
"caught"
|
||||
Done:
|
||||
"done"
|
||||
|
||||
#Vectors
|
||||
|
||||
GuardViolation refusalHandler
|
||||
@@ -0,0 +1,132 @@
|
||||
; Giving a bank number to a device's memory.
|
||||
;
|
||||
; This is the whole sequence an OS goes through: ask the bus registry which ports bring
|
||||
; memory, give one of them a bank number, and then reach it with the controller like any
|
||||
; other bank. A device's memory is unreachable until it has a number, and the controller
|
||||
; is the only thing that can reach it even then.
|
||||
;
|
||||
; How big the bank is comes from the device rather than from this program. Capacity was
|
||||
; settled when the machine was built, so software asserting it could only ever be wrong.
|
||||
;
|
||||
; The device on port 0x12 owns 256 bytes and fills them with whatever byte is written to
|
||||
; its port, which stands in for a disk controller reading a sector.
|
||||
;
|
||||
; Correct output is:
|
||||
; flags 01 the registry says port 0x12 brings memory
|
||||
; 01 12 01 00 bank 5's record: present, owned by port 0x12, 256 bytes
|
||||
; 5A 5A the device's memory, reached through the controller
|
||||
; refused registering over one of the machine's own banks
|
||||
; refused and registering memory from a port that brings none
|
||||
|
||||
#Include print.asm
|
||||
|
||||
#Program
|
||||
|
||||
start:
|
||||
; Ask the registry whether port 0x12 brings memory.
|
||||
INIA 0x12
|
||||
OUTA 0xFF
|
||||
INA 0xFF ; Class, which we do not need here.
|
||||
INA 0xFF ; Flags: bit 0 says it brings memory.
|
||||
PSHA
|
||||
SETD.0 Flags
|
||||
CALL printString
|
||||
CALL blankSpace
|
||||
POPA
|
||||
CALL printByteHex
|
||||
CALL lineFeed
|
||||
|
||||
; Tell the device to fill its memory, the way a disk controller would be told to read.
|
||||
INIA 0x5A
|
||||
OUTA 0x12
|
||||
|
||||
; Give that memory bank number 5.
|
||||
INIA 0d5
|
||||
OUTA 0xE3 ; DestBank = 5, the number being handed out.
|
||||
INIA 0x12
|
||||
OUTA 0xE2 ; SourceLow = the port that owns it.
|
||||
INIA 0x03
|
||||
OUTA 0xE8 ; RegisterBank.
|
||||
|
||||
; Read bank 5's record out of the bank table. Eight bytes a bank, so bank 5 is at 40.
|
||||
INIA 0d2
|
||||
OUTA 0xE0
|
||||
RSTA
|
||||
OUTA 0xE1
|
||||
INIA 0d40
|
||||
OUTA 0xE2
|
||||
CALL readAndPrint ; Flags: present.
|
||||
CALL readAndPrint ; Owner: port 0x12.
|
||||
CALL readAndPrint ; Capacity, high byte.
|
||||
CALL readAndPrint ; Capacity, low byte.
|
||||
CALL lineFeed
|
||||
|
||||
; Now reach the device's memory the way any other bank is reached.
|
||||
INIA 0d5
|
||||
OUTA 0xE0
|
||||
RSTA
|
||||
OUTA 0xE1
|
||||
OUTA 0xE2
|
||||
CALL readAndPrint
|
||||
CALL readAndPrint
|
||||
CALL lineFeed
|
||||
|
||||
; Banks 0 to 2 are the machine's own and cannot be handed out.
|
||||
INIA 0d1
|
||||
OUTA 0xE3
|
||||
INIA 0x12
|
||||
OUTA 0xE2
|
||||
INIA 0x03
|
||||
OUTA 0xE8 ; Refused.
|
||||
|
||||
; Neither can memory from a port that brings none. Port 0x10 is the test device.
|
||||
INIA 0d6
|
||||
OUTA 0xE3
|
||||
INIA 0x10
|
||||
OUTA 0xE2
|
||||
INIA 0x03
|
||||
OUTA 0xE8 ; Refused.
|
||||
HALT
|
||||
|
||||
readAndPrint:
|
||||
INA 0xE9
|
||||
CALL printByteHex
|
||||
CALL blankSpace
|
||||
RET
|
||||
|
||||
; Both refusals arrive here, and they really are the same fault: a bank that cannot be
|
||||
; registered, for two different reasons. Saying so twice is more honest than inventing a
|
||||
; distinction the machine does not draw.
|
||||
bankHandler:
|
||||
SETD.0 Refused
|
||||
CALL printString
|
||||
CALL lineFeed
|
||||
|
||||
; Step past the refused command write, which is an opcode and a port.
|
||||
MVSD.0
|
||||
DPUP.0 0d14
|
||||
LDA.0
|
||||
CCF
|
||||
INIB 0d2
|
||||
ADD
|
||||
MVQA
|
||||
STA.0
|
||||
BRC bankCarried
|
||||
RETI
|
||||
bankCarried:
|
||||
DPDN.0 0d01
|
||||
LDA.0
|
||||
INCA
|
||||
STA.0
|
||||
RETI
|
||||
|
||||
#Data
|
||||
|
||||
Flags:
|
||||
"flags"
|
||||
Refused:
|
||||
"refused"
|
||||
|
||||
#Vectors
|
||||
|
||||
BankFault bankHandler
|
||||
Reference in New Issue
Block a user