Give the memory controller to a bus rather than to the machine
The third and largest piece of the peripheral core, and like the two before it nothing changes: 169 tests, and the two that would notice a misroute pass loudest of all. A CONTROLLER IS THE MOST STATEFUL THING ON THIS MACHINE - a source bank and address, a destination, a length, five guard registers and a table describing every bank it can reach. Two processors sharing one would interleave into nonsense: one sets a source, the other sets a destination, the first issues a blit and moves the wrong bytes somewhere else again. No arbitration fixes that, because there is nothing to arbitrate - both writes were legal and the result belongs to neither of them. So it is a struct threaded through all seventeen functions that touch it, rather than a pointer to a current one set on the way in. The smaller change was tempting and is the shape that produced the stale reset flag and the editor's IsNew surviving a second run, both this week: state that has to be set on the right path before anything reads it. A controller is where that goes wrong quietly rather than loudly. THE STATICS WERE DELETED RATHER THAN LEFT, which is what made this safe to do mechanically. A missed reference is a compile error rather than a variable that still exists and serves the wrong core, so "did I catch all 165?" stopped being a judgement and became a question the compiler answered. Two things the transformation nearly got wrong, both caught by reading rather than by building. guardStart and guardEnd are fields of Bank as well as registers of the controller, so banks[n].guardStart had to keep its name while a bare guardStart changed - the difference between a fence and the register about to be written into one. And a definition and a call look alike enough that the first attempt turned publishBank(number) into publishBank(Controller *c, number); definitions start at column zero here and calls never do. Tests/agree.sh is what says this is right, more than the count does. It builds the same disk with SplitDisk and with CosmOS and compares byte for byte, and every filesystem operation on the machine goes through the controller - so a blit that went to the wrong place would corrupt a disk that is checked against one built by different code entirely. Tests/cycles.sh covers the other half, since what a transfer costs depends on pendingCycles landing in the right one. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01E2JrLzFvuFX9fgi1LDRjrW
This commit is contained in:
Anachronaut
co-authored by
Claude Opus 5
Claude Opus 5
parent
5be5bea994
commit
33afc20abc
+150
-172
@@ -14,152 +14,130 @@
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#include "../Assembler/assembly.h" // For the fault vector numbers.
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#include <string.h>
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typedef struct {
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uint8_t *memory; // Never published. See the note in controller.h.
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uint32_t capacity; // In bytes. A full bank is 65536, which is why this is not 16 bit.
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uint8_t flags;
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uint8_t ownerPort;
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uint16_t guardStart;
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uint16_t guardEnd;
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} Bank;
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static Bank banks[BANK_COUNT];
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// Bank 2's contents: the description of every bank, for anything that wants to read it.
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static uint8_t bankTable[BANK_TABLE_BYTES];
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// The registers, exactly as the ports name them.
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static uint8_t sourceBank, destBank, guardBank;
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static uint16_t sourceAddress, destAddress, length;
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static uint16_t guardStart, guardEnd;
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static uint8_t status;
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// Writes a bank's description into the table that bank 2 publishes. Called whenever
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// anything about a bank changes, so the published table and the real one cannot drift.
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static void publishBank(int number) {
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uint8_t *record = bankTable + number * BANK_RECORD_BYTES;
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record[0] = banks[number].flags;
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record[1] = banks[number].ownerPort;
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static void publishBank(Controller *c, int number) {
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uint8_t *record = c->bankTable + number * BANK_RECORD_BYTES;
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record[0] = c->banks[number].flags;
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record[1] = c->banks[number].ownerPort;
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// Zero means the whole 64K, the same convention Length uses, because a capacity of
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// nothing is never what anyone meant.
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record[2] = (uint8_t)((banks[number].capacity >> 8) & 0xFF);
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record[3] = (uint8_t)(banks[number].capacity & 0xFF);
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record[4] = (uint8_t)(banks[number].guardStart >> 8);
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record[5] = (uint8_t)(banks[number].guardStart & 0xFF);
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record[6] = (uint8_t)(banks[number].guardEnd >> 8);
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record[7] = (uint8_t)(banks[number].guardEnd & 0xFF);
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record[2] = (uint8_t)((c->banks[number].capacity >> 8) & 0xFF);
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record[3] = (uint8_t)(c->banks[number].capacity & 0xFF);
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record[4] = (uint8_t)(c->banks[number].guardStart >> 8);
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record[5] = (uint8_t)(c->banks[number].guardStart & 0xFF);
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record[6] = (uint8_t)(c->banks[number].guardEnd >> 8);
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record[7] = (uint8_t)(c->banks[number].guardEnd & 0xFF);
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}
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static void defineBank(int number, uint8_t *memory, uint32_t capacity, uint8_t flags, uint8_t owner) {
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banks[number].memory = memory;
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banks[number].capacity = capacity;
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banks[number].flags = flags | BANK_FLAG_PRESENT;
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banks[number].ownerPort = owner;
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banks[number].guardStart = 0;
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banks[number].guardEnd = 0;
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publishBank(number);
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static void defineBank(Controller *c, int number, uint8_t *memory, uint32_t capacity, uint8_t flags, uint8_t owner) {
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c->banks[number].memory = memory;
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c->banks[number].capacity = capacity;
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c->banks[number].flags = flags | BANK_FLAG_PRESENT;
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c->banks[number].ownerPort = owner;
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c->banks[number].guardStart = 0;
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c->banks[number].guardEnd = 0;
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publishBank(c, number);
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}
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void initializeController(uint8_t *programMemory, uint8_t *dataMemory) {
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memset(banks, 0, sizeof(banks));
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memset(bankTable, 0, sizeof(bankTable));
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void initializeController(Controller *c, uint8_t *programMemory, uint8_t *dataMemory) {
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memset(c->banks, 0, sizeof(c->banks));
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memset(c->bankTable, 0, sizeof(c->bankTable));
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for (int i = 0; i < BANK_COUNT; i++) {
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banks[i].ownerPort = BANK_OWNER_MACHINE;
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publishBank(i);
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c->banks[i].ownerPort = BANK_OWNER_MACHINE;
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publishBank(c, i);
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}
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defineBank(BANK_PROGRAM, programMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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defineBank(BANK_DATA, dataMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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defineBank(c, BANK_PROGRAM, programMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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defineBank(c, BANK_DATA, dataMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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// The table describes itself, so a program that walks it finds bank 2 in there along
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// with everything else. It is read only, which is what keeps RegisterBank the only
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// way to change what the controller routes through.
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defineBank(BANK_TABLE, bankTable, BANK_TABLE_BYTES, BANK_FLAG_READ_ONLY, BANK_OWNER_MACHINE);
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defineBank(c, BANK_TABLE, c->bankTable, BANK_TABLE_BYTES, BANK_FLAG_READ_ONLY, BANK_OWNER_MACHINE);
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sourceBank = destBank = guardBank = 0;
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sourceAddress = destAddress = length = 0;
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guardStart = guardEnd = 0;
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status = 0;
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c->sourceBank = c->destBank = c->guardBank = 0;
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c->sourceAddress = c->destAddress = c->length = 0;
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c->guardStart = c->guardEnd = 0;
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c->status = 0;
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}
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// Refuses, remembering why so that Status can be read afterwards.
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static void refuse(uint8_t faultVector) {
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status = faultVector;
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static void refuse(Controller *c, uint8_t faultVector) {
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c->status = faultVector;
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refuseAccess(faultVector);
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}
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// Is this somewhere the controller can read? A bank has to be there, and the address has
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// to be inside it.
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static int canRead(uint8_t bank, uint16_t address) {
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if (!(banks[bank].flags & BANK_FLAG_PRESENT) || address >= banks[bank].capacity) {
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refuse(VECTOR_BANK_FAULT);
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static int canRead(Controller *c, uint8_t bank, uint16_t address) {
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if (!(c->banks[bank].flags & BANK_FLAG_PRESENT) || address >= c->banks[bank].capacity) {
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refuse(c, VECTOR_BANK_FAULT);
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return 0;
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}
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return 1;
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}
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// The same, and then the two reasons a write in particular gets turned away.
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static int canWrite(uint8_t bank, uint16_t address) {
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if (!canRead(bank, address)) {
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static int canWrite(Controller *c, uint8_t bank, uint16_t address) {
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if (!canRead(c, bank, address)) {
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(VECTOR_GUARD_VIOLATION);
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if (c->banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(c, VECTOR_GUARD_VIOLATION);
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return 0;
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}
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if ((banks[bank].flags & BANK_FLAG_GUARDED)
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&& address >= banks[bank].guardStart && address <= banks[bank].guardEnd) {
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refuse(VECTOR_GUARD_VIOLATION);
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if ((c->banks[bank].flags & BANK_FLAG_GUARDED)
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&& address >= c->banks[bank].guardStart && address <= c->banks[bank].guardEnd) {
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refuse(c, VECTOR_GUARD_VIOLATION);
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return 0;
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}
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return 1;
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}
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// A length of zero means the whole 64K, because a transfer of no bytes is never what
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// A c->length of zero means the whole 64K, because a transfer of no bytes is never what
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// anyone meant, and 65536 does not fit in the two bytes that carry it.
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static uint32_t transferLength(void) {
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return (length == 0) ? 0x10000u : (uint32_t)length;
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static uint32_t transferLength(Controller *c) {
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return (c->length == 0) ? 0x10000u : (uint32_t)c->length;
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}
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// Everything a transfer will touch is checked before any of it moves. A blit that ran
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// out of bank halfway would leave memory in a state no program asked for, and the
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// diagnostic would arrive after the damage rather than instead of it. So these answer
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// for the whole range or refuse the whole thing.
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static int rangeReadable(uint8_t bank, uint16_t address, uint32_t count) {
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if (!(banks[bank].flags & BANK_FLAG_PRESENT)
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|| (uint32_t)address + count > banks[bank].capacity) {
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refuse(VECTOR_BANK_FAULT);
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static int rangeReadable(Controller *c, uint8_t bank, uint16_t address, uint32_t count) {
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if (!(c->banks[bank].flags & BANK_FLAG_PRESENT)
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|| (uint32_t)address + count > c->banks[bank].capacity) {
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refuse(c, VECTOR_BANK_FAULT);
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return 0;
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}
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return 1;
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}
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static int rangeWritable(uint8_t bank, uint16_t address, uint32_t count) {
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if (!rangeReadable(bank, address, count)) {
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static int rangeWritable(Controller *c, uint8_t bank, uint16_t address, uint32_t count) {
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if (!rangeReadable(c, bank, address, count)) {
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(VECTOR_GUARD_VIOLATION);
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if (c->banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(c, VECTOR_GUARD_VIOLATION);
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_GUARDED) {
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if (c->banks[bank].flags & BANK_FLAG_GUARDED) {
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uint32_t last = (uint32_t)address + count - 1;
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// Any overlap at all with the fence, not just a write that starts inside it.
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if (!(last < banks[bank].guardStart || address > banks[bank].guardEnd)) {
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refuse(VECTOR_GUARD_VIOLATION);
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if (!(last < c->banks[bank].guardStart || address > c->banks[bank].guardEnd)) {
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refuse(c, VECTOR_GUARD_VIOLATION);
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return 0;
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}
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}
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return 1;
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}
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// What the moves below have cost since anybody last asked.
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static unsigned long pendingCycles = 0;
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// ---- Sixteen bits wide, when the addresses let it be ----
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//
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// The controller reaches bank memory two bytes at a time, so an aligned transfer moves two
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// bytes in the time a misaligned one moves one. A word is read at an even address and
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// written at an even address, which is why the source, the destination AND the length must
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// written at an even address, which is why the source, the destination AND the c->length must
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// all be even: an odd anything would have the controller shifting bytes across word
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// boundaries to line them up, and that is a second design rather than this one.
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//
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@@ -173,140 +151,140 @@ static int wideRun(uint32_t addressesAndLength) {
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return (addressesAndLength & 1u) == 0;
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}
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unsigned long controllerTakeCycles(void) {
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unsigned long taken = pendingCycles;
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pendingCycles = 0;
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unsigned long controllerTakeCycles(Controller *c) {
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unsigned long taken = c->pendingCycles;
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c->pendingCycles = 0;
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return taken;
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}
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static void doBlit(void) {
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uint32_t count = transferLength();
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if (!rangeReadable(sourceBank, sourceAddress, count)) {
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static void doBlit(Controller *c) {
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uint32_t count = transferLength(c);
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if (!rangeReadable(c, c->sourceBank, c->sourceAddress, count)) {
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return;
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}
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if (!rangeWritable(destBank, destAddress, count)) {
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if (!rangeWritable(c, c->destBank, c->destAddress, count)) {
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return;
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}
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// memmove rather than memcpy, because source and destination may be the same bank
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// and may overlap. Sliding a buffer along itself is an ordinary thing to want, and
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// getting it silently wrong is exactly the sort of failure this machine keeps
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// designing against.
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memmove(banks[destBank].memory + destAddress,
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banks[sourceBank].memory + sourceAddress, count);
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// A word read and a word written. Two banks are two memories and the pair overlaps;
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memmove(c->banks[c->destBank].memory + c->destAddress,
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c->banks[c->sourceBank].memory + c->sourceAddress, count);
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// A word read and a word written. Two c->banks are two memories and the pair overlaps;
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// one bank is one memory and they do not. The odd cycle is the pipeline filling.
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//
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// Wide when everything is even, so an aligned move between banks settles at two bytes a
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// Wide when everything is even, so an aligned move between c->banks settles at two bytes a
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// cycle and an aligned move within one at a byte a cycle - each twice what it was.
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unsigned long moves = wideRun(sourceAddress | destAddress | count) ? count / 2 : count;
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pendingCycles += (sourceBank == destBank) ? 2 * moves + 1 : moves + 1;
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sourceAddress = (uint16_t)(sourceAddress + count);
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destAddress = (uint16_t)(destAddress + count);
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status = 0;
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unsigned long moves = wideRun(c->sourceAddress | c->destAddress | count) ? count / 2 : count;
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c->pendingCycles += (c->sourceBank == c->destBank) ? 2 * moves + 1 : moves + 1;
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c->sourceAddress = (uint16_t)(c->sourceAddress + count);
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c->destAddress = (uint16_t)(c->destAddress + count);
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c->status = 0;
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}
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static void doFill(void) {
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uint32_t count = transferLength();
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if (!rangeWritable(destBank, destAddress, count)) {
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static void doFill(Controller *c) {
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uint32_t count = transferLength(c);
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if (!rangeWritable(c, c->destBank, c->destAddress, count)) {
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return;
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}
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// A fill has nowhere to read from, only a value, so SourceLow carries the byte and the
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// rest of the source registers mean nothing here - including for the alignment, which
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// asks only about where the bytes are going and how many there are.
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pendingCycles += (wideRun(destAddress | count) ? count / 2 : count) + 1;
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memset(banks[destBank].memory + destAddress, (int)(sourceAddress & 0xFF), count);
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destAddress = (uint16_t)(destAddress + count);
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status = 0;
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c->pendingCycles += (wideRun(c->destAddress | count) ? count / 2 : count) + 1;
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memset(c->banks[c->destBank].memory + c->destAddress, (int)(c->sourceAddress & 0xFF), count);
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c->destAddress = (uint16_t)(c->destAddress + count);
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c->status = 0;
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}
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// DestBank is the number being given out, and SourceLow says which port owns the memory.
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// The capacity is asked of the device rather than supplied, because how big a bank is
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// was settled when the machine was built.
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static void doRegisterBank(void) {
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if (destBank <= BANK_TABLE) {
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static void doRegisterBank(Controller *c) {
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if (c->destBank <= BANK_TABLE) {
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// Banks 0 to 2 are the machine's own and are not anybody's to hand out.
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refuse(VECTOR_BANK_FAULT);
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refuse(c, VECTOR_BANK_FAULT);
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return;
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}
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uint8_t port = (uint8_t)(sourceAddress & 0xFF);
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uint8_t port = (uint8_t)(c->sourceAddress & 0xFF);
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uint32_t capacity = 0;
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uint8_t *memory = deviceMemory(port, &capacity);
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if (memory == NULL) {
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// Either nothing is on that port or what is there brings no memory. Registering
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// it would put a bank in the table that leads nowhere.
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refuse(VECTOR_BANK_FAULT);
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refuse(c, VECTOR_BANK_FAULT);
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return;
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}
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// Registering over a bank that already has something in it is allowed. Which number
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// a device's memory answers to is the OS's business, and nothing was allocated that
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// could be lost by changing its mind.
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defineBank(destBank, memory, capacity, 0, port);
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status = 0;
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defineBank(c, c->destBank, memory, capacity, 0, port);
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c->status = 0;
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}
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// The guard registers stage a range; this is what commits it. Raising a fence over a
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// bank that is not there would protect nothing while looking like it protected
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// something, so it is refused rather than quietly accepted.
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static void doGuardOn(void) {
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if (!(banks[guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(VECTOR_BANK_FAULT);
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static void doGuardOn(Controller *c) {
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if (!(c->banks[c->guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(c, VECTOR_BANK_FAULT);
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return;
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}
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if (guardStart > guardEnd) {
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if (c->guardStart > c->guardEnd) {
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// No address can be inside a range that ends before it starts, so this fence
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// would catch nothing. A program that raised one would believe it was protected
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// and would not be, which is worse than having no fence at all.
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refuse(VECTOR_BANK_FAULT);
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refuse(c, VECTOR_BANK_FAULT);
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return;
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}
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banks[guardBank].guardStart = guardStart;
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banks[guardBank].guardEnd = guardEnd;
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banks[guardBank].flags |= BANK_FLAG_GUARDED;
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publishBank(guardBank);
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status = 0;
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c->banks[c->guardBank].guardStart = c->guardStart;
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c->banks[c->guardBank].guardEnd = c->guardEnd;
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c->banks[c->guardBank].flags |= BANK_FLAG_GUARDED;
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publishBank(c, c->guardBank);
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c->status = 0;
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}
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static void doGuardOff(void) {
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if (!(banks[guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(VECTOR_BANK_FAULT);
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static void doGuardOff(Controller *c) {
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if (!(c->banks[c->guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(c, VECTOR_BANK_FAULT);
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return;
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}
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banks[guardBank].flags &= (uint8_t)~BANK_FLAG_GUARDED;
|
||||
publishBank(guardBank);
|
||||
status = 0;
|
||||
c->banks[c->guardBank].flags &= (uint8_t)~BANK_FLAG_GUARDED;
|
||||
publishBank(c, c->guardBank);
|
||||
c->status = 0;
|
||||
}
|
||||
|
||||
uint8_t controllerWrite(uint8_t value, uint8_t port) {
|
||||
uint8_t controllerWrite(Controller *c, uint8_t value, uint8_t port) {
|
||||
switch (port) {
|
||||
case CTRL_SOURCE_BANK: sourceBank = value; break;
|
||||
case CTRL_SOURCE_HIGH: sourceAddress = (uint16_t)(value << 8) | (sourceAddress & 0x00FF); break;
|
||||
case CTRL_SOURCE_LOW: sourceAddress = (sourceAddress & 0xFF00) | value; break;
|
||||
case CTRL_DEST_BANK: destBank = value; break;
|
||||
case CTRL_DEST_HIGH: destAddress = (uint16_t)(value << 8) | (destAddress & 0x00FF); break;
|
||||
case CTRL_DEST_LOW: destAddress = (destAddress & 0xFF00) | value; break;
|
||||
case CTRL_LENGTH_HIGH: length = (uint16_t)(value << 8) | (length & 0x00FF); break;
|
||||
case CTRL_LENGTH_LOW: length = (length & 0xFF00) | value; break;
|
||||
case CTRL_SOURCE_BANK: c->sourceBank = value; break;
|
||||
case CTRL_SOURCE_HIGH: c->sourceAddress = (uint16_t)(value << 8) | (c->sourceAddress & 0x00FF); break;
|
||||
case CTRL_SOURCE_LOW: c->sourceAddress = (c->sourceAddress & 0xFF00) | value; break;
|
||||
case CTRL_DEST_BANK: c->destBank = value; break;
|
||||
case CTRL_DEST_HIGH: c->destAddress = (uint16_t)(value << 8) | (c->destAddress & 0x00FF); break;
|
||||
case CTRL_DEST_LOW: c->destAddress = (c->destAddress & 0xFF00) | value; break;
|
||||
case CTRL_LENGTH_HIGH: c->length = (uint16_t)(value << 8) | (c->length & 0x00FF); break;
|
||||
case CTRL_LENGTH_LOW: c->length = (c->length & 0xFF00) | value; break;
|
||||
|
||||
case CTRL_GUARD_BANK: guardBank = value; break;
|
||||
case CTRL_GUARD_START_HIGH: guardStart = (uint16_t)(value << 8) | (guardStart & 0x00FF); break;
|
||||
case CTRL_GUARD_START_LOW: guardStart = (guardStart & 0xFF00) | value; break;
|
||||
case CTRL_GUARD_END_HIGH: guardEnd = (uint16_t)(value << 8) | (guardEnd & 0x00FF); break;
|
||||
case CTRL_GUARD_END_LOW: guardEnd = (guardEnd & 0xFF00) | value; break;
|
||||
case CTRL_GUARD_BANK: c->guardBank = value; break;
|
||||
case CTRL_GUARD_START_HIGH: c->guardStart = (uint16_t)(value << 8) | (c->guardStart & 0x00FF); break;
|
||||
case CTRL_GUARD_START_LOW: c->guardStart = (c->guardStart & 0xFF00) | value; break;
|
||||
case CTRL_GUARD_END_HIGH: c->guardEnd = (uint16_t)(value << 8) | (c->guardEnd & 0x00FF); break;
|
||||
case CTRL_GUARD_END_LOW: c->guardEnd = (c->guardEnd & 0xFF00) | value; break;
|
||||
|
||||
case CTRL_DATA:
|
||||
// A byte into the destination, and the address steps on so that writing a
|
||||
// run of bytes is a loop over one instruction rather than four.
|
||||
if (canWrite(destBank, destAddress)) {
|
||||
pendingCycles++; // The byte itself, beyond reaching the port.
|
||||
banks[destBank].memory[destAddress] = value;
|
||||
if (destBank == BANK_TABLE) {
|
||||
if (canWrite(c, c->destBank, c->destAddress)) {
|
||||
c->pendingCycles++; // The byte itself, beyond reaching the port.
|
||||
c->banks[c->destBank].memory[c->destAddress] = value;
|
||||
if (c->destBank == BANK_TABLE) {
|
||||
// Unreachable while the table is read only, and here so that it stays
|
||||
// true if that ever changes: the published bytes are a description,
|
||||
// and nothing may write through them into a real bank.
|
||||
publishBank(BANK_TABLE);
|
||||
publishBank(c, BANK_TABLE);
|
||||
}
|
||||
destAddress++;
|
||||
status = 0;
|
||||
c->destAddress++;
|
||||
c->status = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -314,16 +292,16 @@ uint8_t controllerWrite(uint8_t value, uint8_t port) {
|
||||
// Both leave the addresses past whatever they touched and Length as it was,
|
||||
// so asking again carries straight on from where the last one stopped.
|
||||
switch (value) {
|
||||
case COMMAND_BLIT: doBlit(); break;
|
||||
case COMMAND_FILL: doFill(); break;
|
||||
case COMMAND_REGISTER_BANK: doRegisterBank(); break;
|
||||
case COMMAND_GUARD_ON: doGuardOn(); break;
|
||||
case COMMAND_GUARD_OFF: doGuardOff(); break;
|
||||
case COMMAND_BLIT: doBlit(c); break;
|
||||
case COMMAND_FILL: doFill(c); break;
|
||||
case COMMAND_REGISTER_BANK: doRegisterBank(c); break;
|
||||
case COMMAND_GUARD_ON: doGuardOn(c); break;
|
||||
case COMMAND_GUARD_OFF: doGuardOff(c); break;
|
||||
default:
|
||||
// Refusing an unknown command is better than ignoring it, since a
|
||||
// program that asked for something is entitled to find out that it
|
||||
// did not happen.
|
||||
refuse(VECTOR_BANK_FAULT);
|
||||
refuse(c, VECTOR_BANK_FAULT);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@@ -335,33 +313,33 @@ uint8_t controllerWrite(uint8_t value, uint8_t port) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t controllerRead(uint8_t port) {
|
||||
uint8_t controllerRead(Controller *c, uint8_t port) {
|
||||
switch (port) {
|
||||
case CTRL_SOURCE_BANK: return sourceBank;
|
||||
case CTRL_SOURCE_HIGH: return (uint8_t)(sourceAddress >> 8);
|
||||
case CTRL_SOURCE_LOW: return (uint8_t)(sourceAddress & 0xFF);
|
||||
case CTRL_DEST_BANK: return destBank;
|
||||
case CTRL_DEST_HIGH: return (uint8_t)(destAddress >> 8);
|
||||
case CTRL_DEST_LOW: return (uint8_t)(destAddress & 0xFF);
|
||||
case CTRL_LENGTH_HIGH: return (uint8_t)(length >> 8);
|
||||
case CTRL_LENGTH_LOW: return (uint8_t)(length & 0xFF);
|
||||
case CTRL_STATUS: return status;
|
||||
case CTRL_SOURCE_BANK: return c->sourceBank;
|
||||
case CTRL_SOURCE_HIGH: return (uint8_t)(c->sourceAddress >> 8);
|
||||
case CTRL_SOURCE_LOW: return (uint8_t)(c->sourceAddress & 0xFF);
|
||||
case CTRL_DEST_BANK: return c->destBank;
|
||||
case CTRL_DEST_HIGH: return (uint8_t)(c->destAddress >> 8);
|
||||
case CTRL_DEST_LOW: return (uint8_t)(c->destAddress & 0xFF);
|
||||
case CTRL_LENGTH_HIGH: return (uint8_t)(c->length >> 8);
|
||||
case CTRL_LENGTH_LOW: return (uint8_t)(c->length & 0xFF);
|
||||
case CTRL_STATUS: return c->status;
|
||||
|
||||
case CTRL_GUARD_BANK: return guardBank;
|
||||
case CTRL_GUARD_START_HIGH: return (uint8_t)(guardStart >> 8);
|
||||
case CTRL_GUARD_START_LOW: return (uint8_t)(guardStart & 0xFF);
|
||||
case CTRL_GUARD_END_HIGH: return (uint8_t)(guardEnd >> 8);
|
||||
case CTRL_GUARD_END_LOW: return (uint8_t)(guardEnd & 0xFF);
|
||||
case CTRL_GUARD_BANK: return c->guardBank;
|
||||
case CTRL_GUARD_START_HIGH: return (uint8_t)(c->guardStart >> 8);
|
||||
case CTRL_GUARD_START_LOW: return (uint8_t)(c->guardStart & 0xFF);
|
||||
case CTRL_GUARD_END_HIGH: return (uint8_t)(c->guardEnd >> 8);
|
||||
case CTRL_GUARD_END_LOW: return (uint8_t)(c->guardEnd & 0xFF);
|
||||
|
||||
case CTRL_DATA: {
|
||||
// A byte out of the source, stepping on the same way a write does.
|
||||
if (!canRead(sourceBank, sourceAddress)) {
|
||||
if (!canRead(c, c->sourceBank, c->sourceAddress)) {
|
||||
return 0;
|
||||
}
|
||||
pendingCycles++; // As above, the other way round.
|
||||
uint8_t value = banks[sourceBank].memory[sourceAddress];
|
||||
sourceAddress++;
|
||||
status = 0;
|
||||
c->pendingCycles++; // As above, the other way round.
|
||||
uint8_t value = c->banks[c->sourceBank].memory[c->sourceAddress];
|
||||
c->sourceAddress++;
|
||||
c->status = 0;
|
||||
return value;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user