Anachronaut
c3188ed657
HALT is terminal - stepCPU returns at once when the Halt Flag is up, so a halted machine does not execute, service devices, or take an interrupt - and that has to stay true, because every test ends with a halt and "halted" is how a program says it has finished. The consequence was that SplitBit had no way to wait at all. Every wait was a spin, and a spin is bus traffic: 11.5% of Type over a 14K file on a disk of ten thousand cycles, after read-ahead had already hidden three quarters of the latency. WAIT is 0xFE, one byte, no operands, sitting under HALT where the instruction that almost stops the machine belongs. Three decisions in it: - A line already standing means there is nothing to wait for, so WAIT does nothing. That is what makes test-then-wait race-free. - Any line ends the wait, masked or not, so a program can sleep on a device it has no handler for and read its status afterwards. Masking says who answers a request, not whether it happened. - A line that wakes the CPU without being dispatched is taken down by the WAIT. Left standing it would be found by the next WAIT, which would return at once - the program would spin exactly as before while looking as though it slept. Waiting is NOT a Status bit, and that is the trap avoided rather than a gap: Status rides into the interrupt frame and comes back out, so a machine interrupted mid-wait would return from its handler still waiting, and wait again for what it had already been given. An internal field instead. Idle cycles are counted apart from bus cycles and the halt line says so when there are any, which is what makes the difference observable at all - with the line-clearing removed the total moves by ONE cycle, 20,100 against 20,099, and only the idle half changes, halving to 9,976. A test on totals could never have seen it. Tests/terminal.sh asks that question, being the file for things a recorded output cannot see, and fails with the clear removed while "both reads finished" still passes. Three collisions, all found by building it: - 0xFE was the assembler's "not an instruction" sentinel. getOpcode now answers a negative NOT_AN_OPCODE, which is outside the range of every possible answer instead of inside the unused part of it. - 0xFE was also what faultTest and faultResumeTest executed to provoke a fault. They now use 0xFD and say why, because they did not fail when it became an instruction - they HUNG, having started sleeping instead. - Keys.asm has had a label called "wait" for a year, and mnemonics are matched uppercased. What that reported was "Branch without label" at the BRQ thirty lines away. The assembler now refuses a label that is already an instruction, at the label, by name; every instruction added takes a word out of the space of label names, so this will happen again.
158 lines
4.0 KiB
C
158 lines
4.0 KiB
C
// assembly.c
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// These are functions useful for translating assembly mnemonics to hex and vice-versa for the SplitBit CPU.
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// Written by Anachronaut
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// 10/18/2024
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#include "assembly.h"
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#include <string.h>
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typedef struct {
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uint8_t opcode;
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const char* mnemonic;
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} Instruction;
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Instruction instruction_set[] = {
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// Arithmetic and Logic Operations:
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{0x00, "ADD"},
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{0x01, "SUB"},
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{0x02, "AND"},
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{0x03, "OR"},
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{0x04, "XOR"},
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{0x05, "NOTA"},
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{0x06, "NOTB"},
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{0x07, "SHL"},
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{0x08, "SHR"},
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// Branch Operations:
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{0x10, "BRI"},
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{0x11, "BRQ"},
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{0x12, "BRA"},
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{0x13, "BRB"},
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{0x14, "BRC"},
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{0x15, "BRD"},
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// The same four conditions the other way round. A quarter of the conditional
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// branches in the corpus were a branch over an unconditional one before these
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// existed, each of them needing a label invented only to be jumped past.
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{0x1A, "BNQ"},
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{0x1B, "BNA"},
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{0x1C, "BNB"},
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{0x1D, "BNC"},
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{0x16, "RCAL"},
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{0x17, "CALL"},
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{0x18, "SWI"},
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{0x19, "RETI"},
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{0x1E, "RRET"},
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{0x1F, "RET"},
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// Register Operations:
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{0x20, "RSTA"},
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{0x21, "RSTB"},
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{0x22, "INCA"},
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{0x23, "INCB"},
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{0x24, "DECA"},
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{0x25, "DECB"},
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{0x26, "INIA"},
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{0x27, "INIB"},
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{0x28, "CCF"},
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{0x29, "MVQA"},
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{0x2A, "MVQB"},
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{0x2B, "SIF"},
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{0x2C, "CIF"},
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// Stack Operations:
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{0x30, "PSHQ"},
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{0x31, "PSHA"},
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{0x32, "PSHB"},
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{0x33, "PSHD"},
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{0x34, "POPA"},
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{0x35, "POPB"},
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{0x36, "POPD"},
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// Data Operations:
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{0x40, "INCD"},
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{0x41, "DECD"},
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{0x42, "LDA"},
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{0x43, "LDB"},
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{0x44, "STQ"},
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{0x45, "STA"},
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{0x46, "STB"},
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{0x47, "SETD"},
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{0x48, "DPUP"},
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{0x49, "DPDN"},
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{0x4A, "LDD"},
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{0x4B, "STD"},
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{0x4C, "MVSD"},
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{0x4D, "MVDS"},
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{0x4E, "DPUA"},
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{0x4F, "DPDA"},
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{0x50, "DPUW"},
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{0x51, "DPDW"},
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// Output Operations:
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{0xD0, "OUTQ"},
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{0xD1, "OUTA"},
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{0xD2, "OUTB"},
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// Input Operations:
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{0xE0, "INA"},
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{0xE1, "INB"},
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// Special Operations:
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{0xF0, "NOP"},
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{0xFE, "WAIT"},
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{0xFF, "HALT"}
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};
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int num_instructions = sizeof(instruction_set) / sizeof(Instruction);
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const char* getMnemonic(uint8_t opcode) {
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for (int i = 0; i < num_instructions; i++) {
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if (instruction_set[i].opcode == opcode) {
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return instruction_set[i].mnemonic;
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}
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}
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return "---";
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}
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int dataPointerOperands(uint8_t opcode) {
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// How many Data Pointer selector bytes follow this opcode. Most instructions
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// have none. The ones that work through a pointer have one naming which pointer.
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// LDD and STD move a pointer through a pointer, so they name two.
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switch (opcode) {
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case 0x4A: // LDD
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case 0x4B: // STD
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return 2;
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case 0x15: // BRD
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case 0x33: // PSHD
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case 0x36: // POPD
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case 0x40: // INCD
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case 0x41: // DECD
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case 0x42: // LDA
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case 0x43: // LDB
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case 0x44: // STQ
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case 0x45: // STA
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case 0x46: // STB
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case 0x47: // SETD
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case 0x48: // DPUP
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case 0x49: // DPDN
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case 0x4C: // MVSD
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case 0x4D: // MVDS
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case 0x4E: // DPUA
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case 0x4F: // DPDA
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case 0x50: // DPUW
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case 0x51: // DPDW
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return 1;
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default:
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return 0;
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}
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}
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int getOpcode(char* mnemonic) {
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for (int i = 0; i < num_instructions; i++) {
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if (strcmp(instruction_set[i].mnemonic, mnemonic) == 0) {
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return instruction_set[i].opcode;
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}
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}
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// NOT_AN_OPCODE, and it is negative on purpose. This used to answer 0xFE on the
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// grounds that 0xFE was unused - which was true until WAIT was given that opcode, at
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// which point the assembler would have read WAIT as a word it did not recognise. A
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// sentinel picked from the unused half of a range stops being a sentinel the moment
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// somebody uses the range, so this one is outside the range altogether.
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return NOT_AN_OPCODE;
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}
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