AnachronautandClaude Opus 5
4c3eac8d9c
The controller now reaches bank memory two bytes at a time, so a transfer whose source, destination and length are all even moves two bytes a cycle between banks and one within a bank - twice what each was. A 256 byte block between banks falls from 257 cycles to 129. Alignment is required all three ways because a word is read at an even address and written at an even address; an odd anything would mean shifting bytes across word boundaries to line them up, which is a different design. A misaligned transfer falls back to the byte a cycle it cost before, so nothing already written got slower. THE CPU DOES NOT CHANGE. It still sees eight bits, a Data Pointer still addresses a byte, and no instruction means anything different. This is a peripheral getting faster, which is why it is worth doing now rather than after more is built on top of it. The rule is deliberately visible rather than smoothed over: aligning a buffer costs nothing and halves what moving it costs, and a cost a program cannot see is a cost it cannot avoid. Tests/cycles.sh is new, and is the test the Test Manual has always said this kind of change would need - run.sh strips the cycle count from every recorded result, so nothing else in the suite can see any of this. It pins the RATE rather than a total: each case runs twice from programs whose instructions are identical but for the byte written to the Command port, once asking for the transfer and once for GuardOff, which costs nothing beyond the port write. The difference is the transfer and nothing else. Verified by disabling the widening, which failed exactly the three aligned cases and left the five misaligned ones passing. The Programming Manual gains a section saying what a transfer costs, which it never said at all - it only promised a transfer does not wait, which is a different claim and could be read as promising it is free. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01E2JrLzFvuFX9fgi1LDRjrW
119 lines
4.6 KiB
C
119 lines
4.6 KiB
C
// controller.h
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// The SplitBit Memory Controller.
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// Written by Anachronaut
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#ifndef CONTROLLER_H
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#define CONTROLLER_H
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#include <stdint.h>
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// ---- Ports ----
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//
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// Sixteen registers, one to a port, written and read directly. A register file behind a
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// single port would be smaller but stateful, and losing your place in a device that
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// moves memory corrupts memory rather than an answer.
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#define CONTROLLER_PORT_BASE 0xE0
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#define CONTROLLER_PORT_TOP 0xEF
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#define CTRL_SOURCE_BANK 0xE0
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#define CTRL_SOURCE_HIGH 0xE1
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#define CTRL_SOURCE_LOW 0xE2
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#define CTRL_DEST_BANK 0xE3
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#define CTRL_DEST_HIGH 0xE4
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#define CTRL_DEST_LOW 0xE5
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#define CTRL_LENGTH_HIGH 0xE6
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#define CTRL_LENGTH_LOW 0xE7
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#define CTRL_COMMAND 0xE8
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#define CTRL_DATA 0xE9
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#define CTRL_STATUS 0xEA
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#define CTRL_GUARD_BANK 0xEB
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#define CTRL_GUARD_START_HIGH 0xEC
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#define CTRL_GUARD_START_LOW 0xED
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#define CTRL_GUARD_END_HIGH 0xEE
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#define CTRL_GUARD_END_LOW 0xEF
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// ---- Commands ----
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//
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// Written to the Command port, which performs them at once. A blit is instantaneous from
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// the CPU's point of view: waiting belongs to the peripheral that has something to wait
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// for, not to the moving of bytes.
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#define COMMAND_BLIT 0x01
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#define COMMAND_FILL 0x02
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// Gives a bank number to the memory owned by a device. How big it is comes from the
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// device, not from software: a program asserting a hardware fact could only ever be
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// wrong about it.
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#define COMMAND_REGISTER_BANK 0x03
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// Raises and lowers the fence over the bank named by GuardBank. Any program may do
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// either: this is a fence rather than a wall, and nobody is ever told no. What it stops
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// is walking into something by accident, not walking into it on purpose.
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#define COMMAND_GUARD_ON 0x10
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#define COMMAND_GUARD_OFF 0x11
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// ---- Banks ----
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//
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// Program and Data are banks like any other; being banks 0 and 1 is the only thing
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// special about them. Bank 2 is the controller's own memory, and the bank table lives
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// in it, which is how anything finds out what banks exist without a second protocol.
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#define BANK_PROGRAM 0
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#define BANK_DATA 1
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#define BANK_TABLE 2
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#define BANK_COUNT 256
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// Eight bytes each, so bank n's record begins at n * 8.
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//
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// 0 Flags
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// 1 The port that owns it, or the machine itself for banks 0 to 2
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// 2 - 3 Capacity, where zero means the whole 64K
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// 4 - 5 First guarded address
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// 6 - 7 Last guarded address
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//
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// What is published is a description. The pointer a bank really holds is never in here:
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// a program that could write one would be setting a host address, which means nothing on
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// hardware and everything to the emulator running it.
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#define BANK_RECORD_BYTES 8
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#define BANK_TABLE_BYTES (BANK_COUNT * BANK_RECORD_BYTES)
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#define BANK_FLAG_PRESENT 0x01
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#define BANK_FLAG_READ_ONLY 0x02
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#define BANK_FLAG_GUARDED 0x04
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// Banks 0 to 2 belong to the machine rather than to any device.
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#define BANK_OWNER_MACHINE 0xFF
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// ---- What the controller's work costs ----
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//
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// The controller moves memory, and memory takes time to move: a byte has to be read from
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// somewhere and written somewhere else. A blit is not free just because the machine issues
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// it with one instruction, and pretending otherwise made a quarter of a millisecond of
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// work look like ten cycles.
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//
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// Banks are separate memories, which is what decides the rate. A move between two of them
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// can overlap its read and its write - fetch the next word while the last one is stored -
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// while a move WITHIN one bank cannot and costs twice as much. A fill has nothing to read
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// and costs the same as a move between banks.
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//
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// AND THE PATH IS SIXTEEN BITS WIDE, so a transfer whose source, destination and length are
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// all even moves two bytes a cycle between banks and one within a bank. Anything odd falls
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// back to the byte a cycle this had before it was widened: lining up bytes across word
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// boundaries is a second design, and this is not it. See wideRun in controller.c.
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//
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// Returned and cleared, so the caller adds it to whatever it is charging for. The CPU picks
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// it up after each port access, which makes the transfer a stall: the machine issues a blit
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// and waits for it. Whether real hardware would let the two run at once is a live question -
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// the memories are separate, so it plausibly could - and the answer wants measuring before
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// it is designed.
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unsigned long controllerTakeCycles(void);
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void initializeController(uint8_t *programMemory, uint8_t *dataMemory);
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uint8_t controllerWrite(uint8_t value, uint8_t port);
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uint8_t controllerRead(uint8_t port);
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#endif // CONTROLLER_H
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