a <address>, then instructions until a line that is just a dot. The syntax is the assembler's own: a selector rides on the mnemonic as LDA.0 or LDD.0.1, and leaving one off means Data Pointer 0 exactly as it does in a source file, so nothing learned at the monitor has to be unlearned when writing a program. Case is folded, since the assembler does not care either. Numbers are hexadecimal and bare. A source file writes 0x2000 or 0d16 because it has both and must say which; a monitor has one and says so once, in the manual, rather than on every line. It reads the same table the disassembler does, searched the other way round, which is the point of it being a table rather than two lists: what a writes, d reads back, and neither can drift from the other or from the assembler both were generated from. Instruction lengths come from the shared shape table too, so the cursor cannot get out of step with what was written. THE WHOLE LINE IS UNDERSTOOD BEFORE ANYTHING IS WRITTEN. Emitting the opcode first and discovering a missing operand afterwards leaves half an instruction in memory, which the next line usually covers up and the last line of a session does not. Written that way first and fixed. What cannot be written is a label, and that is the whole difference between this and the assembler proper: a label is a promise to fill an address in later, and later is what a line at a time does not have. The recorded test now types in a complete program - a string poked into Data Memory, instructions assembled into Program Memory, and the result run - and includes a lower case mnemonic, both selector forms, an instruction that does not exist and one missing its value, so the refusals sit beside the successes. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
35 lines
318 B
Plaintext
35 lines
318 B
Plaintext
monitor
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b nonsense
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b 9
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load greet.sbx
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b program
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d 2000
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x 2000
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b data
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x 1000
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b 2
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x 0
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s 0 FF
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b program
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s 8000 26 48 D1 00 26 0A D1 00 18 12
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d 8000
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g 8000
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d 8000
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b data
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s 8100 68 65 6C 6C 6F 2C 20 74 79 70 65 64 0A 00
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b program
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a 8200
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SETD.0 8100
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SWI 10
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lda.2
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LDD.0.1
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frobnicate
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INIA
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SWI 12
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.
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d 8200
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g 8200
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exit
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dir
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exit
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