Anachronaut
cd5f548736
Three blocks move and nothing else changes. Branches take 0x60, subroutines take 0x70, and the ALU moves up into the 0x10 block the two of them used to share. Order within each block is preserved exactly - this relocates them, it does not rethink them. WHAT IT BUYS IS AN EMPTY 0x00 TO 0x0F. Program Memory that was never written, or a load that stopped part way and left zeroes in its tail, used to read as a long run of ADDs: the machine carried on through them, arrived somewhere unpredictable, and whatever broke there was a long way from the byte that caused it. Now it faults where it is met: Fault: 0x00 at Program Address 0x0004 is not an instruction. That is the address of the byte after the last real instruction, which is the difference between a diagnosis and a search. Reserving the whole nibble rather than just 0x00 means a run into blank memory faults wherever it starts rather than only when it lands on the right byte. runOffTest records it, and the block is left empty for whatever turns out to want it. The other half is room: branches and subroutines had filled 0x10 to 0x1F between them, so a service return that keeps Q and DP3 had nowhere to sit next to its family. It has 0x76 waiting now. Five places wrote an opcode down that the scripted remap did not reach, and four of them were found by tests rather than by looking: - secondPass.c lists which opcodes take an address, and firstPass.c knows SWI by number. Missing those made XOR read as a branch. - Asm.asm knows SWI by number too, being the other assembler. Missing it made the native and host assemblers disagree byte for byte, which is exactly the check that exists to catch a thing known in two places. - loaderTest.asm carries a hand written payload, and its RETI was 0x19. To the assembler those are numbers and to the program they are data, so nothing but running it could notice. It says so in a comment now. - The Assembler Manual prints the bytes hello.asm assembles to, and two of them were branches. The monitor's recorded disassembly moved by exactly the bytes it should: 18 became 72 wherever SWI appears, with SETD and INIB untouched and every disassembled line still reading the same.
172 lines
4.8 KiB
C
172 lines
4.8 KiB
C
// assembly.c
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// These are functions useful for translating assembly mnemonics to hex and vice-versa for the SplitBit CPU.
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// Written by Anachronaut
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// 10/18/2024
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#include "assembly.h"
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#include <string.h>
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typedef struct {
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uint8_t opcode;
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const char* mnemonic;
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} Instruction;
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Instruction instruction_set[] = {
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// ---- Nothing at all in 0x00 to 0x0F ----
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//
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// Kept empty on purpose. Program Memory that has never been written, or a load that
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// stopped part way and left zeroes in its tail, used to read as a long run of
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// additions and then do something unpredictable a long way from the cause. An
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// unassigned byte faults where it is met, with the address, which is the difference
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// between a diagnosis and a search.
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//
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// Arithmetic and Logic Operations:
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{0x10, "ADD"},
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{0x11, "SUB"},
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{0x12, "AND"},
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{0x13, "OR"},
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{0x14, "XOR"},
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{0x15, "NOTA"},
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{0x16, "NOTB"},
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{0x17, "SHL"},
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{0x18, "SHR"},
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// Branch Operations:
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{0x60, "BRI"},
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{0x61, "BRQ"},
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{0x62, "BRA"},
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{0x63, "BRB"},
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{0x64, "BRC"},
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{0x65, "BRD"},
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// The same four conditions the other way round. A quarter of the conditional
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// branches in the corpus were a branch over an unconditional one before these
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// existed, each of them needing a label invented only to be jumped past.
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{0x66, "BNQ"},
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{0x67, "BNA"},
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{0x68, "BNB"},
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{0x69, "BNC"},
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// Subroutine Operations:
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//
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// A block of their own since the branches and these outgrew one nibble between them.
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// Each raw form sits immediately below the ordinary one it cannot be mixed with: RCAL
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// under CALL, RRET under RET, because the frames differ and returning through the
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// wrong one takes the machine somewhere nobody named.
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{0x70, "RCAL"},
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{0x71, "CALL"},
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{0x72, "SWI"},
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{0x73, "RETI"},
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{0x74, "RRET"},
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{0x75, "RET"},
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// Register Operations:
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{0x20, "RSTA"},
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{0x21, "RSTB"},
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{0x22, "INCA"},
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{0x23, "INCB"},
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{0x24, "DECA"},
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{0x25, "DECB"},
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{0x26, "INIA"},
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{0x27, "INIB"},
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{0x28, "CCF"},
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{0x29, "MVQA"},
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{0x2A, "MVQB"},
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{0x2B, "SIF"},
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{0x2C, "CIF"},
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// Stack Operations:
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{0x30, "PSHQ"},
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{0x31, "PSHA"},
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{0x32, "PSHB"},
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{0x33, "PSHD"},
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{0x34, "POPA"},
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{0x35, "POPB"},
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{0x36, "POPD"},
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// Data Operations:
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{0x40, "INCD"},
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{0x41, "DECD"},
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{0x42, "LDA"},
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{0x43, "LDB"},
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{0x44, "STQ"},
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{0x45, "STA"},
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{0x46, "STB"},
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{0x47, "SETD"},
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{0x48, "DPUP"},
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{0x49, "DPDN"},
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{0x4A, "LDD"},
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{0x4B, "STD"},
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{0x4C, "MVSD"},
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{0x4D, "MVDS"},
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{0x4E, "DPUA"},
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{0x4F, "DPDA"},
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{0x50, "DPUW"},
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{0x51, "DPDW"},
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// Output Operations:
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{0xD0, "OUTQ"},
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{0xD1, "OUTA"},
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{0xD2, "OUTB"},
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// Input Operations:
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{0xE0, "INA"},
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{0xE1, "INB"},
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// Special Operations:
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{0xF0, "NOP"},
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{0xFE, "WAIT"},
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{0xFF, "HALT"}
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};
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int num_instructions = sizeof(instruction_set) / sizeof(Instruction);
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const char* getMnemonic(uint8_t opcode) {
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for (int i = 0; i < num_instructions; i++) {
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if (instruction_set[i].opcode == opcode) {
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return instruction_set[i].mnemonic;
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}
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}
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return "---";
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}
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int dataPointerOperands(uint8_t opcode) {
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// How many Data Pointer selector bytes follow this opcode. Most instructions
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// have none. The ones that work through a pointer have one naming which pointer.
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// LDD and STD move a pointer through a pointer, so they name two.
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switch (opcode) {
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case 0x4A: // LDD
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case 0x4B: // STD
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return 2;
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case 0x65: // BRD
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case 0x33: // PSHD
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case 0x36: // POPD
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case 0x40: // INCD
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case 0x41: // DECD
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case 0x42: // LDA
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case 0x43: // LDB
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case 0x44: // STQ
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case 0x45: // STA
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case 0x46: // STB
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case 0x47: // SETD
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case 0x48: // DPUP
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case 0x49: // DPDN
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case 0x4C: // MVSD
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case 0x4D: // MVDS
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case 0x4E: // DPUA
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case 0x4F: // DPDA
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case 0x50: // DPUW
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case 0x51: // DPDW
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return 1;
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default:
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return 0;
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}
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}
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int getOpcode(char* mnemonic) {
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for (int i = 0; i < num_instructions; i++) {
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if (strcmp(instruction_set[i].mnemonic, mnemonic) == 0) {
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return instruction_set[i].opcode;
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}
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}
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// NOT_AN_OPCODE, and it is negative on purpose. This used to answer 0xFE on the
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// grounds that 0xFE was unused - which was true until WAIT was given that opcode, at
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// which point the assembler would have read WAIT as a word it did not recognise. A
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// sentinel picked from the unused half of a range stops being a sentinel the moment
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// somebody uses the range, so this one is outside the range altogether.
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return NOT_AN_OPCODE;
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}
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