Anachronaut
c3188ed657
HALT is terminal - stepCPU returns at once when the Halt Flag is up, so a halted machine does not execute, service devices, or take an interrupt - and that has to stay true, because every test ends with a halt and "halted" is how a program says it has finished. The consequence was that SplitBit had no way to wait at all. Every wait was a spin, and a spin is bus traffic: 11.5% of Type over a 14K file on a disk of ten thousand cycles, after read-ahead had already hidden three quarters of the latency. WAIT is 0xFE, one byte, no operands, sitting under HALT where the instruction that almost stops the machine belongs. Three decisions in it: - A line already standing means there is nothing to wait for, so WAIT does nothing. That is what makes test-then-wait race-free. - Any line ends the wait, masked or not, so a program can sleep on a device it has no handler for and read its status afterwards. Masking says who answers a request, not whether it happened. - A line that wakes the CPU without being dispatched is taken down by the WAIT. Left standing it would be found by the next WAIT, which would return at once - the program would spin exactly as before while looking as though it slept. Waiting is NOT a Status bit, and that is the trap avoided rather than a gap: Status rides into the interrupt frame and comes back out, so a machine interrupted mid-wait would return from its handler still waiting, and wait again for what it had already been given. An internal field instead. Idle cycles are counted apart from bus cycles and the halt line says so when there are any, which is what makes the difference observable at all - with the line-clearing removed the total moves by ONE cycle, 20,100 against 20,099, and only the idle half changes, halving to 9,976. A test on totals could never have seen it. Tests/terminal.sh asks that question, being the file for things a recorded output cannot see, and fails with the clear removed while "both reads finished" still passes. Three collisions, all found by building it: - 0xFE was the assembler's "not an instruction" sentinel. getOpcode now answers a negative NOT_AN_OPCODE, which is outside the range of every possible answer instead of inside the unused part of it. - 0xFE was also what faultTest and faultResumeTest executed to provoke a fault. They now use 0xFD and say why, because they did not fail when it became an instruction - they HUNG, having started sleeping instead. - Keys.asm has had a label called "wait" for a year, and mnemonics are matched uppercased. What that reported was "Branch without label" at the BRQ thirty lines away. The assembler now refuses a label that is already an instruction, at the label, by name; every instruction added takes a word out of the space of label names, so this will happen again.
875 lines
36 KiB
C
875 lines
36 KiB
C
// cpu.c
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// SplitBit CPU Emulator Core
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// Written by Anachronaut
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// 10/16/2024
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#include "cpu.h"
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#include "io.h"
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#include "controller.h"
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#include "../Assembler/assembly.h" // For the vector table layout, which both tools share.
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uint16_t shiftRegister;
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// Reads one entry out of a vector table. Most significant byte first, matching the
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// branch instructions and both file formats.
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// ---- Every touch of memory, and what it costs ----
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//
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// One access, one cycle. These exist so that the cost is counted in the one place the
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// access happens, rather than in a table of per instruction costs kept somewhere else -
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// a table like that is a second copy of what the code does, and the two drift.
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static inline uint8_t fetchProgram(CPURegisters *cpu, uint16_t at) {
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cpu->busCycles++;
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return cpu->Program[at];
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}
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static inline uint8_t readData(CPURegisters *cpu, uint16_t at) {
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cpu->busCycles++;
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return cpu->Data[at];
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}
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static inline void writeData(CPURegisters *cpu, uint16_t at, uint8_t value) {
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cpu->busCycles++;
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cpu->Data[at] = value;
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}
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// A device port is reached over the same bus as memory, so it costs the same. That is a
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// claim about the hardware rather than an observation - a machine could put devices
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// somewhere faster or slower - and it is the simple thing until there is a reason to say
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// otherwise.
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static inline void portOut(CPURegisters *cpu, uint8_t value, uint8_t port) {
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cpu->busCycles++;
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OutputHandler(value, port);
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// And whatever memory that made the controller move. The machine waits for it, which
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// is the conservative reading: a blit stalls the program that asked for one.
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cpu->busCycles += controllerTakeCycles();
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}
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static inline uint8_t portIn(CPURegisters *cpu, uint8_t port) {
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cpu->busCycles++;
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uint8_t value = InputHandler(port);
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cpu->busCycles += controllerTakeCycles();
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return value;
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}
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static uint16_t readVector(const uint8_t *programMemory, uint16_t base, uint8_t index) {
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uint16_t address = base + (uint16_t)index * VECTOR_ENTRY_BYTES;
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return ((uint16_t)programMemory[address] << 8) | (uint16_t)programMemory[address + 1];
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}
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// Builds an interrupt frame and dispatches through a vector. The resume address is the
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// address execution should carry on from once the handler returns, and it goes into the
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// frame as a real address so that a handler can read it and make sense of it.
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//
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// Returns 0 if it dispatched. If the vector is empty there is nothing to dispatch to, so
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// it raises a fault and returns 1 rather than jumping to the bottom of Program Memory
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// and running whatever happens to be there.
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//
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// Note that a zero entry means "no handler" to everything that dispatches, including the
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// two entries the CPU treats as start addresses when it reads them at reset. The
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// exemption belongs to that one read, not to the entries themselves.
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static uint8_t enterInterrupt(CPURegisters *cpu, uint16_t base, uint8_t index, uint16_t resumeAddress) {
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uint16_t handler = readVector(cpu->Program, base, index);
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if (handler == 0x0000) {
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cpu->Fault = FAULT_NO_HANDLER;
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cpu->FaultVector = index;
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cpu->Status |= STATUS_FAULT;
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cpu->Status |= STATUS_HALT;
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return 1;
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}
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// Order mirrors genericCall exactly: low byte then high byte, lowest numbered Data
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// Pointer first, so that anything walking the Stack sees a familiar shape.
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writeData(cpu, cpu->StackPointer, resumeAddress & 0xFF);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, (resumeAddress >> 8) & 0xFF);
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cpu->StackPointer--;
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for (int i = 0; i < DATA_POINTERS; i++) {
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writeData(cpu, cpu->StackPointer, cpu->DataPointer[i] & 0xFF);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, (cpu->DataPointer[i] >> 8) & 0xFF);
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cpu->StackPointer--;
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}
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writeData(cpu, cpu->StackPointer, cpu->B);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, cpu->A);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, cpu->Q);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, cpu->Status);
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cpu->StackPointer--;
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// A handler runs with hardware interrupts held off unless it says otherwise, so an
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// interrupt cannot arrive inside the handler for another one and grow the Stack
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// without bound. The old setting rode into the frame inside the Status register, so
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// RETI puts it back without anything having to remember it separately.
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cpu->Status &= ~STATUS_INTERRUPT;
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// The Program Counter is stepped after every instruction, so land one short of the
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// handler and let that step land on its first byte. genericBranch does the same.
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cpu->ProgramCounter = handler - 1;
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return 0;
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}
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// A device that refused what it was asked stops the machine where it stands, rather than
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// raising a line and letting execution carry on past the mistake. The frame carries the
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// address of the instruction that asked, so a handler can see which one it was, and so a
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// bare RETI meets it again the way every other fault on this machine does.
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//
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// Returns 1 if the machine has stopped because nothing was installed to catch it.
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static uint8_t answerRefusal(CPURegisters *cpu, uint16_t site) {
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uint8_t refusal = takeRefusal();
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if (refusal == 0) {
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return 0;
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}
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if (enterInterrupt(cpu, SOFTWARE_VECTOR_BASE, refusal, site)) {
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cpu->Fault = FAULT_DEVICE_REFUSED;
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cpu->FaultVector = refusingPort();
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cpu->ProgramCounter = site - 1;
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}
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return 0;
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}
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void initializeCPU(CPURegisters *cpu, uint8_t *programMemory, uint8_t *dataMemory) {
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cpu->A = 0;
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cpu->B = 0;
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cpu->Q = 0;
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cpu->Status = 0;
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// Execution begins wherever the boot vector points. It is a start address rather
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// than a handler, so a zero there is not "nothing installed" but the address
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// 0x0000, which is where a program carrying no vector table of its own begins.
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// That is what lets everything written before the table existed still run.
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cpu->ProgramCounter = readVector(programMemory, SOFTWARE_VECTOR_BASE, VECTOR_BOOT);
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// Every Data Pointer starts at the bottom of Data Memory.
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for (int i = 0; i < DATA_POINTERS; i++) {
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cpu->DataPointer[i] = 0x0000;
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}
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cpu->StackPointer = 0xFFFF;
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cpu->Program = programMemory;
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cpu->Data = dataMemory;
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cpu->busCycles = 0;
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cpu->idleCycles = 0;
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cpu->Waiting = 0;
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cpu->Fault = FAULT_NONE;
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cpu->FaultVector = 0;
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}
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void genericBranch(CPURegisters *cpu){
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// Load the next two bytes from program memory into the Program Counter.
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// Byte order is imporant. Most Significant first, then Least Significant.
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cpu->ProgramCounter++; // Move to the next byte. (MSB)
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uint16_t DestinationAddress;
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DestinationAddress = (uint16_t)fetchProgram(cpu, cpu->ProgramCounter) << 8; // Cast the 8 bit value to a 16 bit value and shifts it up to the high byte.
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cpu->ProgramCounter++; // Move to the next byte. (LSB)
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DestinationAddress = DestinationAddress | (uint16_t)fetchProgram(cpu, cpu->ProgramCounter); // Cast the 8 bit value to a 16 bit value and or it to add it to the desination.
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cpu->ProgramCounter = DestinationAddress-1;
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}
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void genericCall(CPURegisters *cpu){
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// Order, low byte, high byte
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writeData(cpu, cpu->StackPointer, cpu->ProgramCounter & 0xFF);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, (cpu->ProgramCounter >> 8) & 0xFF);
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cpu->StackPointer--;
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// Push the preserved Data Pointers to the Stack, lowest numbered first.
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// Order within each one, low byte, high byte.
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// The pointers above PRESERVED_DATA_POINTERS are deliberately left alone, so a
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// subroutine can use one to hand an address back to whoever called it.
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for (int i = 0; i < PRESERVED_DATA_POINTERS; i++) {
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writeData(cpu, cpu->StackPointer, cpu->DataPointer[i] & 0xFF);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, (cpu->DataPointer[i] >> 8) & 0xFF);
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cpu->StackPointer--;
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}
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// Push B to the Stack.
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writeData(cpu, cpu->StackPointer, cpu->B);
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cpu->StackPointer--;
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// Push A to the Stack.
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writeData(cpu, cpu->StackPointer, cpu->A);
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cpu->StackPointer--;
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// Perform a Generic Branch to the Address.
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genericBranch(cpu);
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}
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uint16_t *selectDataPointer(CPURegisters *cpu) {
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// Every instruction that works through a Data Pointer names which one in the
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// byte immediately after the opcode. Out of range selectors are masked down
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// rather than rejected, the way a narrow field in hardware would be. It is the
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// assembler's job to refuse to emit one in the first place.
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cpu->ProgramCounter++;
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return &cpu->DataPointer[fetchProgram(cpu, cpu->ProgramCounter) & (DATA_POINTERS - 1)];
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}
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uint8_t executeOperation(uint8_t Instruction, CPURegisters *cpu) {
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// ADD and SUB share this. It is declared here rather than after a case label
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// because a label may only be followed by a statement in ISO C, and a
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// declaration is not one.
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uint16_t result;
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switch(Instruction) {
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// 0x - Arithmetic and Logic Operations.
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case 0x00:
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// ADD - A + B + Carry -> Q
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result = (uint16_t)cpu->A + (uint16_t)cpu->B + (cpu->Status & STATUS_CARRY);
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if (result > 255) {
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cpu->Status |= STATUS_CARRY;
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} else {
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cpu->Status &= ~STATUS_CARRY;
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}
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cpu->Q = result & 0xFF;
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break;
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case 0x01:
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// SUB - A - B - Carry -> Q
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result = (uint16_t)cpu->A - (uint16_t)cpu->B - (cpu->Status & STATUS_CARRY);
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if (result > 255) {
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cpu->Status |= STATUS_CARRY;
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} else {
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cpu->Status &= ~STATUS_CARRY;
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}
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cpu->Q = result & 0xFF;
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break;
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case 0x02:
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// AND - A and B -> Q
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cpu->Q = cpu->A&cpu->B;
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break;
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case 0x03:
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// OR - A or B -> Q
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cpu->Q = cpu->A|cpu->B;
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break;
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case 0x04:
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// XOR - A xor B -> Q
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cpu->Q = cpu->A^cpu->B;
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break;
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case 0x05:
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// NOTA - not A -> Q
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cpu->Q = ~cpu->A;
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break;
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case 0x06:
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// NOTB - not B -> Q
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cpu->Q = ~cpu->B;
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break;
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case 0x07:
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// SHL - Shift AB left.
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shiftRegister = ((uint16_t)cpu->A << 8) | cpu->B;
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shiftRegister = (shiftRegister << 1) | (shiftRegister >> 15);
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cpu->A = shiftRegister >> 8;
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cpu->B = shiftRegister & 0xFF;
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break;
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case 0x08:
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// SHR - Shift AB right.
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shiftRegister = ((uint16_t)cpu->A << 8) | cpu->B;
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shiftRegister = (shiftRegister >> 1) | (shiftRegister << 15);
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cpu->A = shiftRegister >> 8;
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cpu->B = shiftRegister & 0xFF;
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break;
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//
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// 1x - Branch Operations:
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//
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case 0x10:
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// BRI - Branch Immediately
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genericBranch(cpu);
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break;
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case 0x11:
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// BRQ - Branch if Q = 0
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if(cpu->Q == 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x12:
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// BRA - Branch if A = 0
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if(cpu->A == 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x13:
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// BRB - if B = 0
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if(cpu->B == 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x14:
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// BRC - Do an immediate branch if the Carry Flag is set.
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if (cpu->Status & STATUS_CARRY) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x15: {
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// BRD - Branch to the address held in a Data Pointer.
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// This is the only branch whose destination is not written into the
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// program, which is what makes a table of addresses something a program
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// can dispatch through rather than only read.
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uint16_t destination = *selectDataPointer(cpu);
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// stepCPU adds one after every instruction, so aim one short.
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cpu->ProgramCounter = destination - 1;
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}
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break;
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case 0x16:
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// RCAL - Call, pushing nothing but the return address.
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//
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// The unsafe one, and it says so in its name. CALL puts A, B and the first
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// three Data Pointers back the way it found them, which costs ten bytes of
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// Stack and means a subroutine can only hand anything back through Q, DP3 or
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// memory. RCAL costs two bytes and puts nothing back at all: everything the
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// callee touches, the caller has lost.
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//
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// It must be returned from with RRET. The two frames are different sizes, so
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// returning from one through the other walks the Stack to somewhere that was
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// never a return address.
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writeData(cpu, cpu->StackPointer, cpu->ProgramCounter & 0xFF);
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cpu->StackPointer--;
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writeData(cpu, cpu->StackPointer, (cpu->ProgramCounter >> 8) & 0xFF);
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cpu->StackPointer--;
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genericBranch(cpu);
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break;
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case 0x17:
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// CALL - Push the Program Counter to the Stack, and perform an immediate branch.
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genericCall(cpu);
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break;
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case 0x1A:
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// BNQ - Branch if Q is not 0.
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if(cpu->Q != 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x1B:
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// BNA - Branch if A is not 0.
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if(cpu->A != 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x1C:
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// BNB - Branch if B is not 0.
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if(cpu->B != 0) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x1D:
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// BNC - Branch if the Carry Flag is clear.
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if (!(cpu->Status & STATUS_CARRY)) {
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genericBranch(cpu);
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} else {
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cpu->ProgramCounter+=2;
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}
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break;
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case 0x18: {
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// SWI - Software Interrupt. The byte after the opcode names the vector.
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// Never masked: this is an instruction the program deliberately ran, not
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// something a device asked for.
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uint16_t site = cpu->ProgramCounter;
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cpu->ProgramCounter++;
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uint8_t vector = fetchProgram(cpu, cpu->ProgramCounter);
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// Execution resumes after the operand, which the Program Counter is sitting
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// on, so the resume address is one further on than that.
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if (enterInterrupt(cpu, SOFTWARE_VECTOR_BASE, vector, cpu->ProgramCounter + 1)) {
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// No handler. Leave the Program Counter on the SWI itself rather than
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// its operand, so the report names the instruction that failed.
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cpu->ProgramCounter = site - 1;
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}
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} break;
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case 0x19: {
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// RETI - Return from an interrupt. Pops the frame in the exact reverse of
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// the order enterInterrupt pushed it.
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cpu->StackPointer++;
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cpu->Status = readData(cpu, cpu->StackPointer);
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cpu->StackPointer++;
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cpu->Q = readData(cpu, cpu->StackPointer);
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cpu->StackPointer++;
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cpu->A = readData(cpu, cpu->StackPointer);
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cpu->StackPointer++;
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cpu->B = readData(cpu, cpu->StackPointer);
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for (int i = DATA_POINTERS - 1; i >= 0; i--) {
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cpu->StackPointer++;
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cpu->DataPointer[i] = (uint16_t)readData(cpu, cpu->StackPointer) << 8;
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cpu->StackPointer++;
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cpu->DataPointer[i] |= (uint16_t)readData(cpu, cpu->StackPointer);
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}
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uint16_t resumeAddress;
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cpu->StackPointer++;
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resumeAddress = (uint16_t)readData(cpu, cpu->StackPointer) << 8;
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cpu->StackPointer++;
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resumeAddress = resumeAddress | (uint16_t)readData(cpu, cpu->StackPointer);
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// The frame holds the address to carry on from. The Program Counter is
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// stepped after every instruction, so land one short of it. RET does the
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// same job with its +2, for the same reason.
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cpu->ProgramCounter = resumeAddress - 1;
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} break;
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case 0x1E:
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// RRET - Return from an RCAL, taking back nothing but the return address.
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cpu->StackPointer++;
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cpu->ProgramCounter = (uint16_t)readData(cpu, cpu->StackPointer) << 8;
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cpu->StackPointer++;
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cpu->ProgramCounter = cpu->ProgramCounter | (uint16_t)readData(cpu, cpu->StackPointer);
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// Two on, to step over the address the RCAL branched through, exactly as RET
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// does. Everything else RET restores, this deliberately does not.
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cpu->ProgramCounter += 2;
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break;
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case 0x1F:
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// RET - Return from subroutine, restore the registers and set the Program Counter to the Return Address.
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// Pop A from the Stack.
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cpu->StackPointer++;
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cpu->A = readData(cpu, cpu->StackPointer);
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// Pop B from the Stack.
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cpu->StackPointer++;
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cpu->B = readData(cpu, cpu->StackPointer);
|
|
// Pop the preserved Data Pointers from the Stack. This walks the pointers
|
|
// in the opposite order to genericCall, and takes the high byte before the
|
|
// low byte, so that it exactly mirrors the way they were pushed.
|
|
for (int i = PRESERVED_DATA_POINTERS - 1; i >= 0; i--) {
|
|
cpu->StackPointer++;
|
|
cpu->DataPointer[i] = (uint16_t)readData(cpu, cpu->StackPointer) << 8;
|
|
cpu->StackPointer++;
|
|
cpu->DataPointer[i] |= (uint16_t)readData(cpu, cpu->StackPointer);
|
|
}
|
|
// Pop the Return Address from the Stack.
|
|
cpu->StackPointer++;
|
|
cpu->ProgramCounter = (uint16_t)readData(cpu, cpu->StackPointer) << 8;
|
|
cpu->StackPointer++;
|
|
cpu->ProgramCounter = cpu->ProgramCounter | (uint16_t)readData(cpu, cpu->StackPointer);
|
|
// Add 2 to the Program Counter to skip over the address when it returns.
|
|
cpu->ProgramCounter += 2;
|
|
|
|
break;
|
|
//
|
|
// 2x - Register Operations:
|
|
//
|
|
case 0x20:
|
|
// RSTA - Reset A to 0.
|
|
cpu->A = 0;
|
|
break;
|
|
case 0x21:
|
|
// RSTB - Reset B to 0.
|
|
cpu->B = 0;
|
|
break;
|
|
case 0x22:
|
|
// INCA - Add 1 to A.
|
|
// Set the Carry Flag if the register overflows.
|
|
if (cpu->A == 0xFF) {
|
|
cpu->Status |= STATUS_CARRY;
|
|
} else {
|
|
cpu->Status &= ~STATUS_CARRY;
|
|
}
|
|
cpu->A++;
|
|
break;
|
|
case 0x23:
|
|
// INCB - Add 1 to B.
|
|
// Set the Carry Flag if the register overflows.
|
|
if (cpu->B == 0xFF) {
|
|
cpu->Status |= STATUS_CARRY;
|
|
} else {
|
|
cpu->Status &= ~STATUS_CARRY;
|
|
}
|
|
cpu->B++;
|
|
break;
|
|
case 0x24:
|
|
// DECA - Subtract 1 from A.
|
|
// Set the Carry Flag if the register underflows.
|
|
if (cpu->A == 0x00) {
|
|
cpu->Status |= STATUS_CARRY;
|
|
} else {
|
|
cpu->Status &= ~STATUS_CARRY;
|
|
}
|
|
cpu->A--;
|
|
break;
|
|
case 0x25:
|
|
// DECB - Subtract 1 from B.
|
|
// Set the Carry Flag if the register underflows.
|
|
if (cpu->B == 0x00) {
|
|
cpu->Status |= STATUS_CARRY;
|
|
} else {
|
|
cpu->Status &= ~STATUS_CARRY;
|
|
}
|
|
cpu->B--;
|
|
break;
|
|
case 0x26:
|
|
// INIA - Initialize A Immediately from Program Memory.
|
|
cpu->ProgramCounter++;
|
|
cpu->A = fetchProgram(cpu, cpu->ProgramCounter);
|
|
break;
|
|
case 0x27:
|
|
// INIB - Initialize A Immediately from Program Memory.
|
|
cpu->ProgramCounter++;
|
|
cpu->B = fetchProgram(cpu, cpu->ProgramCounter);
|
|
break;
|
|
case 0x28:
|
|
// CCF - Clear the Carry Flag.
|
|
cpu->Status &= ~STATUS_CARRY;
|
|
break;
|
|
case 0x29:
|
|
// MVQA - Copy Q into A.
|
|
cpu->A = cpu->Q;
|
|
break;
|
|
case 0x2A:
|
|
// MVQB - Copy Q into B.
|
|
cpu->B = cpu->Q;
|
|
break;
|
|
case 0x2B:
|
|
// SIF - Set the Interrupt Flag, enabling hardware interrupts.
|
|
cpu->Status |= STATUS_INTERRUPT;
|
|
break;
|
|
case 0x2C:
|
|
// CIF - Clear the Interrupt Flag, disabling hardware interrupts.
|
|
// Software interrupts and faults are delivered either way, so this
|
|
// only ever holds off a device.
|
|
cpu->Status &= ~STATUS_INTERRUPT;
|
|
break;
|
|
//
|
|
// 3x - Stack Operations:
|
|
//
|
|
case 0x30:
|
|
// PSHQ - Push Q to the Stack.
|
|
writeData(cpu, cpu->StackPointer, cpu->Q);
|
|
cpu->StackPointer--;
|
|
break;
|
|
case 0x31:
|
|
// PSHA - Push A to the Stack.
|
|
writeData(cpu, cpu->StackPointer, cpu->A);
|
|
cpu->StackPointer--;
|
|
break;
|
|
case 0x32:
|
|
// PSHB - Push B to the Stack.
|
|
writeData(cpu, cpu->StackPointer, cpu->B);
|
|
cpu->StackPointer--;
|
|
break;
|
|
case 0x33: {
|
|
// PSHD - Push the selected Data Pointer Address to the Stack.
|
|
// Order, high byte, low byte
|
|
// This ordering makes it easier to add offsets with register math.
|
|
uint16_t pushed = *selectDataPointer(cpu);
|
|
writeData(cpu, cpu->StackPointer, (pushed >> 8) & 0xFF);
|
|
cpu->StackPointer--;
|
|
writeData(cpu, cpu->StackPointer, pushed & 0xFF);
|
|
cpu->StackPointer--;
|
|
}
|
|
break;
|
|
case 0x34:
|
|
// POPA - Pop A from the Stack.
|
|
cpu->StackPointer++;
|
|
cpu->A = readData(cpu, cpu->StackPointer);
|
|
|
|
break;
|
|
case 0x35:
|
|
// POPB - Pop B from the Stack.
|
|
cpu->StackPointer++;
|
|
cpu->B = readData(cpu, cpu->StackPointer);
|
|
break;
|
|
case 0x36: {
|
|
// POPD - Pop a Data Address from the Stack into the selected Data Pointer.
|
|
uint16_t *popped = selectDataPointer(cpu);
|
|
cpu->StackPointer++;
|
|
*popped = (uint16_t)readData(cpu, cpu->StackPointer);
|
|
cpu->StackPointer++;
|
|
*popped |= (uint16_t)readData(cpu, cpu->StackPointer) << 8;
|
|
}
|
|
break;
|
|
//
|
|
// 4x - Data Operations:
|
|
//
|
|
case 0x40:
|
|
// INCD - Increment the selected Data Pointer.
|
|
(*selectDataPointer(cpu))++;
|
|
break;
|
|
case 0x41:
|
|
// DECD - Decrement the selected Data Pointer.
|
|
(*selectDataPointer(cpu))--;
|
|
break;
|
|
case 0x42:
|
|
// LDA - Load A from Data.
|
|
cpu->A = readData(cpu, *selectDataPointer(cpu));
|
|
break;
|
|
case 0x43:
|
|
// LDB - Load B from Data.
|
|
cpu->B = readData(cpu, *selectDataPointer(cpu));
|
|
break;
|
|
case 0x44:
|
|
// STQ - Store Q into Data.
|
|
writeData(cpu, *selectDataPointer(cpu), cpu->Q);
|
|
break;
|
|
case 0x45:
|
|
// STA - Store A into Data.
|
|
writeData(cpu, *selectDataPointer(cpu), cpu->A);
|
|
break;
|
|
case 0x46:
|
|
// STB - Store B into Data.
|
|
writeData(cpu, *selectDataPointer(cpu), cpu->B);
|
|
break;
|
|
case 0x47: {
|
|
// SETD - Set the selected Data Pointer.
|
|
uint16_t *destination = selectDataPointer(cpu);
|
|
cpu->ProgramCounter++;
|
|
uint16_t Address;
|
|
Address = (uint16_t)fetchProgram(cpu, cpu->ProgramCounter) << 8; // Cast the 8 bits to a 16 bit value and shift them to the high byte.
|
|
cpu->ProgramCounter++;
|
|
Address |= (uint16_t)fetchProgram(cpu, cpu->ProgramCounter);
|
|
*destination = Address;
|
|
}
|
|
break;
|
|
case 0x48: {
|
|
// DPUP - Offset the selected Data Pointer up by the value of the next byte of Program Memory.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
cpu->ProgramCounter++;
|
|
*target += fetchProgram(cpu, cpu->ProgramCounter);
|
|
}
|
|
break;
|
|
case 0x49: {
|
|
// DPDN - Offset the selected Data Pointer down by the value of the next byte of Program Memory.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
cpu->ProgramCounter++;
|
|
*target -= fetchProgram(cpu, cpu->ProgramCounter);
|
|
}
|
|
break;
|
|
case 0x4E: {
|
|
// DPUA - Offset the selected Data Pointer up by A.
|
|
//
|
|
// A rather than Q, because Q is what the ALU last worked out and would be
|
|
// gone by the time anything had been added to it. Working a step out and then
|
|
// moving a pointer by it took a store and a reload before this existed.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
*target += cpu->A;
|
|
}
|
|
break;
|
|
case 0x4F: {
|
|
// DPDA - Offset the selected Data Pointer down by A.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
*target -= cpu->A;
|
|
}
|
|
break;
|
|
case 0x50: {
|
|
// DPUW - Offset the selected Data Pointer up by A and B together, A being the
|
|
// most significant, which is how every sixteen bit value on this machine is
|
|
// carried between a pair of registers.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
*target += ((uint16_t)cpu->A << 8) | (uint16_t)cpu->B;
|
|
}
|
|
break;
|
|
case 0x51: {
|
|
// DPDW - Offset the selected Data Pointer down by A and B together.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
*target -= ((uint16_t)cpu->A << 8) | (uint16_t)cpu->B;
|
|
}
|
|
break;
|
|
case 0x4A: {
|
|
// LDD - Load the first Data Pointer from the two bytes of Data Memory
|
|
// addressed by the second. Byte order matches everywhere else an address
|
|
// is stored: most significant first, then least significant.
|
|
// The source is taken by value before anything is written, so LDD.0.0
|
|
// follows the pointer in DP0 rather than tripping over itself.
|
|
uint16_t *destination = selectDataPointer(cpu);
|
|
uint16_t source = *selectDataPointer(cpu);
|
|
*destination = (uint16_t)readData(cpu, source) << 8;
|
|
*destination |= (uint16_t)readData(cpu, (uint16_t)(source + 1));
|
|
}
|
|
break;
|
|
case 0x4B: {
|
|
// STD - Store the first Data Pointer into the two bytes of Data Memory
|
|
// addressed by the second. The cast on the second address keeps it inside
|
|
// Data Memory when the pointer sits at the very top of it.
|
|
uint16_t value = *selectDataPointer(cpu);
|
|
uint16_t address = *selectDataPointer(cpu);
|
|
writeData(cpu, address, (value >> 8) & 0xFF);
|
|
writeData(cpu, (uint16_t)(address + 1), value & 0xFF);
|
|
}
|
|
break;
|
|
case 0x4C: {
|
|
// MVSD - Copy the Stack Pointer into the selected Data Pointer.
|
|
//
|
|
// The Stack Pointer still cannot be written, so this does not let a program
|
|
// move the Stack. It lets a program find it, which is what reading anything
|
|
// already on the Stack requires. An interrupt handler needs this to reach
|
|
// its own frame, and so does anything that wants to walk back through the
|
|
// calls that led to where it is.
|
|
uint16_t *target = selectDataPointer(cpu);
|
|
*target = cpu->StackPointer;
|
|
}
|
|
break;
|
|
case 0x4D: {
|
|
// MVDS - Copy the selected Data Pointer into the Stack Pointer.
|
|
//
|
|
// This one is dangerous and is meant to be used rarely. Moving the Stack
|
|
// under a running program abandons every return address on it, so a RET
|
|
// after this goes wherever the new Stack happens to say.
|
|
//
|
|
// It exists because a system that runs other programs has no other way to
|
|
// get its Stack back. A program that gives up part way through leaves
|
|
// whatever it pushed behind, and the interrupt frame that carried the
|
|
// request to stop is on there too. Without this the Stack only ever grows
|
|
// downward, one abandoned program at a time, and a shell cannot outlive
|
|
// many of them.
|
|
uint16_t *source = selectDataPointer(cpu);
|
|
cpu->StackPointer = *source;
|
|
}
|
|
break;
|
|
//
|
|
// Dx - Output Operations:
|
|
//
|
|
case 0xD0: {
|
|
// OUTQ - Write the value of Q to an output port.
|
|
uint16_t site = cpu->ProgramCounter;
|
|
cpu->ProgramCounter++;
|
|
portOut(cpu, cpu->Q, fetchProgram(cpu, cpu->ProgramCounter));
|
|
answerRefusal(cpu, site);
|
|
}
|
|
break;
|
|
case 0xD1: {
|
|
// OUTA - Write the value of A to an output port.
|
|
uint16_t site = cpu->ProgramCounter;
|
|
cpu->ProgramCounter++;
|
|
portOut(cpu, cpu->A, fetchProgram(cpu, cpu->ProgramCounter));
|
|
answerRefusal(cpu, site);
|
|
}
|
|
break;
|
|
case 0xD2: {
|
|
// OUTB - Write the value of B to an output port.
|
|
uint16_t site = cpu->ProgramCounter;
|
|
cpu->ProgramCounter++;
|
|
portOut(cpu, cpu->B, fetchProgram(cpu, cpu->ProgramCounter));
|
|
answerRefusal(cpu, site);
|
|
}
|
|
break;
|
|
//
|
|
// Ex - Input Operations:
|
|
//
|
|
case 0xE0: {
|
|
// INA - Read an Input to A.
|
|
uint16_t site = cpu->ProgramCounter;
|
|
cpu->ProgramCounter++;
|
|
cpu->A = portIn(cpu, fetchProgram(cpu, cpu->ProgramCounter));
|
|
answerRefusal(cpu, site);
|
|
}
|
|
break;
|
|
case 0xE1: {
|
|
// INB - Read an Input to B.
|
|
uint16_t site = cpu->ProgramCounter;
|
|
cpu->ProgramCounter++;
|
|
cpu->B = portIn(cpu, fetchProgram(cpu, cpu->ProgramCounter));
|
|
answerRefusal(cpu, site);
|
|
}
|
|
break;
|
|
//
|
|
// Fx - Special Operations:
|
|
//
|
|
case 0xF0:
|
|
// NOP - Do nothing.
|
|
break;
|
|
case 0xFE:
|
|
// WAIT - Stop fetching until a device asks for attention.
|
|
//
|
|
// NOT A HALT. The machine is still clocked and devices still run; what stops
|
|
// is the CPU's use of the bus. HALT is how a program says it has finished and
|
|
// must stay that way, so this is a separate instruction rather than a gentler
|
|
// HALT - and its state is a field of its own rather than a Status bit, for
|
|
// the reason cpu.h gives.
|
|
//
|
|
// A LINE ALREADY UP MEANS THERE IS NOTHING TO WAIT FOR, and that is what
|
|
// makes the ordinary idiom race-free: a program tests its device, finds it
|
|
// busy, and waits. If the device finished in between, the line is standing
|
|
// and this does nothing at all rather than sleeping through the answer.
|
|
if (nextPendingInterrupt() < 0) {
|
|
cpu->Waiting = 1;
|
|
}
|
|
break;
|
|
case 0xFF:
|
|
// HALT - Set the Halt Bit of the Status Register.
|
|
cpu->Status |= STATUS_HALT;
|
|
break;
|
|
default:
|
|
// Unknown Instruction.
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void stepCPU(CPURegisters *cpu) {
|
|
if (!(cpu->Status & STATUS_HALT)) {
|
|
// Devices get their moment before the lines are read, and unconditionally: a
|
|
// device is entitled to notice something whether or not the CPU is currently
|
|
// willing to be interrupted about it. Masking decides when a request is answered,
|
|
// not whether the outside world is allowed to have happened.
|
|
serviceDevices();
|
|
// ---- Stopped in a WAIT ----
|
|
//
|
|
// Nothing is fetched and nothing is executed. A clock still passes, because a
|
|
// device that takes time has to be able to reach the end of it, and it is charged
|
|
// to idle rather than to the bus: the CPU is not using memory.
|
|
//
|
|
// A LINE OF ANY KIND ENDS THE WAIT, masked or not. Masking says who answers a
|
|
// request, not whether it happened - so a program can sleep on a device it has no
|
|
// handler for and simply read its status afterwards, which is the whole reason
|
|
// this is worth having and is what the filesystem does with it.
|
|
if (cpu->Waiting) {
|
|
if (nextPendingInterrupt() < 0) {
|
|
cpu->idleCycles++;
|
|
return;
|
|
}
|
|
cpu->Waiting = 0;
|
|
// Woken while masked, so nobody is going to answer this line and take it
|
|
// down. IT HAS TO BE TAKEN DOWN HERE. Left standing it would be found by the
|
|
// next WAIT, which would return at once, and by the one after that - the
|
|
// program would spin exactly as it did before while appearing to sleep.
|
|
//
|
|
// Unmasked, the dispatch below takes it down instead, and a line with no
|
|
// handler faults there the way it always has. Waiting changes what the CPU
|
|
// does between instructions; it does not change interrupt policy.
|
|
if (!(cpu->Status & STATUS_INTERRUPT)) {
|
|
clearInterrupt((uint8_t)nextPendingInterrupt());
|
|
}
|
|
}
|
|
// A device asking for attention is answered between instructions and never
|
|
// inside one, so the address that goes into the frame is always the start of an
|
|
// instruction and RETI always lands somewhere meaningful.
|
|
//
|
|
// A line that is up while the Interrupt Flag is clear stays up. Masking holds a
|
|
// device off; it does not lose what the device was asking for.
|
|
if (cpu->Status & STATUS_INTERRUPT) {
|
|
int port = nextPendingInterrupt();
|
|
if (port >= 0) {
|
|
clearInterrupt((uint8_t)port);
|
|
if (enterInterrupt(cpu, HARDWARE_VECTOR_BASE, (uint8_t)port, cpu->ProgramCounter)) {
|
|
// The device asked and nobody was listening. enterInterrupt has
|
|
// already stopped the machine; correct the cause, because the empty
|
|
// entry is in the hardware table rather than the software one.
|
|
cpu->Fault = FAULT_NO_DEVICE_HANDLER;
|
|
return;
|
|
}
|
|
// Entering the handler is what this cycle did, so no instruction runs.
|
|
// The step puts the Program Counter on the handler's first byte, the
|
|
// same way it does everywhere else.
|
|
cpu->ProgramCounter++;
|
|
return;
|
|
}
|
|
}
|
|
// The CPU is not halted, so do a cycle.
|
|
if (executeOperation(fetchProgram(cpu, cpu->ProgramCounter), cpu)) {
|
|
// Nothing decodes that byte. Hand it to the fault vector, which gets the
|
|
// address of the offending byte itself rather than the one after it, so
|
|
// that a handler can read the byte that failed and say what it was.
|
|
//
|
|
// A handler returning with a bare RETI will therefore meet the same byte
|
|
// again. That is the documented behaviour: resuming past a fault means
|
|
// deciding where to resume, which is the handler's business and not the
|
|
// CPU's guess.
|
|
uint16_t faultingAddress = cpu->ProgramCounter;
|
|
if (enterInterrupt(cpu, SOFTWARE_VECTOR_BASE, VECTOR_INVALID_OPCODE, faultingAddress)) {
|
|
// Nothing is installed, so stop where we are. The Program Counter is
|
|
// still on the offending byte, which is what the report wants. The
|
|
// cause is the byte, not the empty vector, so say so.
|
|
cpu->Fault = FAULT_BAD_OPCODE;
|
|
return;
|
|
}
|
|
// Dispatched. Fall through, so the step below lands on the handler.
|
|
}
|
|
cpu->ProgramCounter++;
|
|
}
|
|
}
|