332 lines
13 KiB
C
332 lines
13 KiB
C
// controller.c
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// The SplitBit Memory Controller.
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//
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// This is the only thing on the machine that can write Program Memory. That is the whole
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// reason it exists: SplitBit is a Harvard machine and its instruction set cannot reach
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// its own code, which is worth keeping true of the instructions. Routing it through a
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// device instead makes writing code a capability, reached deliberately through a port,
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// rather than something every instruction stream can do by accident.
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//
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// Written by Anachronaut
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#include "controller.h"
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#include "io.h"
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#include "../Assembler/assembly.h" // For the fault vector numbers.
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#include <string.h>
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typedef struct {
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uint8_t *memory; // Never published. See the note in controller.h.
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uint32_t capacity; // In bytes. A full bank is 65536, which is why this is not 16 bit.
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uint8_t flags;
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uint8_t ownerPort;
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uint16_t guardStart;
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uint16_t guardEnd;
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} Bank;
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static Bank banks[BANK_COUNT];
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// Bank 2's contents: the description of every bank, for anything that wants to read it.
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static uint8_t bankTable[BANK_TABLE_BYTES];
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// The registers, exactly as the ports name them.
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static uint8_t sourceBank, destBank, guardBank;
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static uint16_t sourceAddress, destAddress, length;
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static uint16_t guardStart, guardEnd;
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static uint8_t status;
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// Writes a bank's description into the table that bank 2 publishes. Called whenever
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// anything about a bank changes, so the published table and the real one cannot drift.
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static void publishBank(int number) {
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uint8_t *record = bankTable + number * BANK_RECORD_BYTES;
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record[0] = banks[number].flags;
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record[1] = banks[number].ownerPort;
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// Zero means the whole 64K, the same convention Length uses, because a capacity of
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// nothing is never what anyone meant.
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record[2] = (uint8_t)((banks[number].capacity >> 8) & 0xFF);
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record[3] = (uint8_t)(banks[number].capacity & 0xFF);
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record[4] = (uint8_t)(banks[number].guardStart >> 8);
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record[5] = (uint8_t)(banks[number].guardStart & 0xFF);
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record[6] = (uint8_t)(banks[number].guardEnd >> 8);
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record[7] = (uint8_t)(banks[number].guardEnd & 0xFF);
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}
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static void defineBank(int number, uint8_t *memory, uint32_t capacity, uint8_t flags, uint8_t owner) {
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banks[number].memory = memory;
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banks[number].capacity = capacity;
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banks[number].flags = flags | BANK_FLAG_PRESENT;
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banks[number].ownerPort = owner;
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banks[number].guardStart = 0;
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banks[number].guardEnd = 0;
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publishBank(number);
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}
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void initializeController(uint8_t *programMemory, uint8_t *dataMemory) {
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memset(banks, 0, sizeof(banks));
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memset(bankTable, 0, sizeof(bankTable));
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for (int i = 0; i < BANK_COUNT; i++) {
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banks[i].ownerPort = BANK_OWNER_MACHINE;
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publishBank(i);
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}
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defineBank(BANK_PROGRAM, programMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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defineBank(BANK_DATA, dataMemory, 0x10000, 0, BANK_OWNER_MACHINE);
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// The table describes itself, so a program that walks it finds bank 2 in there along
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// with everything else. It is read only, which is what keeps RegisterBank the only
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// way to change what the controller routes through.
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defineBank(BANK_TABLE, bankTable, BANK_TABLE_BYTES, BANK_FLAG_READ_ONLY, BANK_OWNER_MACHINE);
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sourceBank = destBank = guardBank = 0;
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sourceAddress = destAddress = length = 0;
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guardStart = guardEnd = 0;
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status = 0;
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}
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// Refuses, remembering why so that Status can be read afterwards.
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static void refuse(uint8_t faultVector) {
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status = faultVector;
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refuseAccess(faultVector);
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}
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// Is this somewhere the controller can read? A bank has to be there, and the address has
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// to be inside it.
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static int canRead(uint8_t bank, uint16_t address) {
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if (!(banks[bank].flags & BANK_FLAG_PRESENT) || address >= banks[bank].capacity) {
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refuse(VECTOR_BANK_FAULT);
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return 0;
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}
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return 1;
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}
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// The same, and then the two reasons a write in particular gets turned away.
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static int canWrite(uint8_t bank, uint16_t address) {
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if (!canRead(bank, address)) {
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(VECTOR_GUARD_VIOLATION);
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return 0;
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}
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if ((banks[bank].flags & BANK_FLAG_GUARDED)
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&& address >= banks[bank].guardStart && address <= banks[bank].guardEnd) {
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refuse(VECTOR_GUARD_VIOLATION);
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return 0;
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}
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return 1;
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}
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// A length of zero means the whole 64K, because a transfer of no bytes is never what
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// anyone meant, and 65536 does not fit in the two bytes that carry it.
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static uint32_t transferLength(void) {
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return (length == 0) ? 0x10000u : (uint32_t)length;
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}
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// Everything a transfer will touch is checked before any of it moves. A blit that ran
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// out of bank halfway would leave memory in a state no program asked for, and the
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// diagnostic would arrive after the damage rather than instead of it. So these answer
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// for the whole range or refuse the whole thing.
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static int rangeReadable(uint8_t bank, uint16_t address, uint32_t count) {
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if (!(banks[bank].flags & BANK_FLAG_PRESENT)
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|| (uint32_t)address + count > banks[bank].capacity) {
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refuse(VECTOR_BANK_FAULT);
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return 0;
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}
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return 1;
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}
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static int rangeWritable(uint8_t bank, uint16_t address, uint32_t count) {
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if (!rangeReadable(bank, address, count)) {
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_READ_ONLY) {
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refuse(VECTOR_GUARD_VIOLATION);
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return 0;
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}
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if (banks[bank].flags & BANK_FLAG_GUARDED) {
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uint32_t last = (uint32_t)address + count - 1;
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// Any overlap at all with the fence, not just a write that starts inside it.
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if (!(last < banks[bank].guardStart || address > banks[bank].guardEnd)) {
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refuse(VECTOR_GUARD_VIOLATION);
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return 0;
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}
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}
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return 1;
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}
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static void doBlit(void) {
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uint32_t count = transferLength();
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if (!rangeReadable(sourceBank, sourceAddress, count)) {
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return;
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}
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if (!rangeWritable(destBank, destAddress, count)) {
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return;
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}
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// memmove rather than memcpy, because source and destination may be the same bank
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// and may overlap. Sliding a buffer along itself is an ordinary thing to want, and
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// getting it silently wrong is exactly the sort of failure this machine keeps
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// designing against.
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memmove(banks[destBank].memory + destAddress,
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banks[sourceBank].memory + sourceAddress, count);
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sourceAddress = (uint16_t)(sourceAddress + count);
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destAddress = (uint16_t)(destAddress + count);
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status = 0;
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}
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static void doFill(void) {
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uint32_t count = transferLength();
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if (!rangeWritable(destBank, destAddress, count)) {
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return;
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}
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// A fill has nowhere to read from, only a value, so SourceLow carries the byte and
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// the rest of the source registers mean nothing here.
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memset(banks[destBank].memory + destAddress, (int)(sourceAddress & 0xFF), count);
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destAddress = (uint16_t)(destAddress + count);
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status = 0;
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}
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// DestBank is the number being given out, and SourceLow says which port owns the memory.
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// The capacity is asked of the device rather than supplied, because how big a bank is
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// was settled when the machine was built.
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static void doRegisterBank(void) {
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if (destBank <= BANK_TABLE) {
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// Banks 0 to 2 are the machine's own and are not anybody's to hand out.
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refuse(VECTOR_BANK_FAULT);
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return;
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}
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uint8_t port = (uint8_t)(sourceAddress & 0xFF);
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uint32_t capacity = 0;
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uint8_t *memory = deviceMemory(port, &capacity);
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if (memory == NULL) {
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// Either nothing is on that port or what is there brings no memory. Registering
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// it would put a bank in the table that leads nowhere.
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refuse(VECTOR_BANK_FAULT);
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return;
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}
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// Registering over a bank that already has something in it is allowed. Which number
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// a device's memory answers to is the OS's business, and nothing was allocated that
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// could be lost by changing its mind.
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defineBank(destBank, memory, capacity, 0, port);
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status = 0;
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}
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// The guard registers stage a range; this is what commits it. Raising a fence over a
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// bank that is not there would protect nothing while looking like it protected
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// something, so it is refused rather than quietly accepted.
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static void doGuardOn(void) {
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if (!(banks[guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(VECTOR_BANK_FAULT);
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return;
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}
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if (guardStart > guardEnd) {
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// No address can be inside a range that ends before it starts, so this fence
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// would catch nothing. A program that raised one would believe it was protected
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// and would not be, which is worse than having no fence at all.
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refuse(VECTOR_BANK_FAULT);
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return;
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}
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banks[guardBank].guardStart = guardStart;
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banks[guardBank].guardEnd = guardEnd;
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banks[guardBank].flags |= BANK_FLAG_GUARDED;
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publishBank(guardBank);
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status = 0;
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}
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static void doGuardOff(void) {
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if (!(banks[guardBank].flags & BANK_FLAG_PRESENT)) {
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refuse(VECTOR_BANK_FAULT);
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return;
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}
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banks[guardBank].flags &= (uint8_t)~BANK_FLAG_GUARDED;
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publishBank(guardBank);
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status = 0;
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}
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uint8_t controllerWrite(uint8_t value, uint8_t port) {
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switch (port) {
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case CTRL_SOURCE_BANK: sourceBank = value; break;
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case CTRL_SOURCE_HIGH: sourceAddress = (uint16_t)(value << 8) | (sourceAddress & 0x00FF); break;
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case CTRL_SOURCE_LOW: sourceAddress = (sourceAddress & 0xFF00) | value; break;
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case CTRL_DEST_BANK: destBank = value; break;
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case CTRL_DEST_HIGH: destAddress = (uint16_t)(value << 8) | (destAddress & 0x00FF); break;
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case CTRL_DEST_LOW: destAddress = (destAddress & 0xFF00) | value; break;
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case CTRL_LENGTH_HIGH: length = (uint16_t)(value << 8) | (length & 0x00FF); break;
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case CTRL_LENGTH_LOW: length = (length & 0xFF00) | value; break;
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case CTRL_GUARD_BANK: guardBank = value; break;
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case CTRL_GUARD_START_HIGH: guardStart = (uint16_t)(value << 8) | (guardStart & 0x00FF); break;
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case CTRL_GUARD_START_LOW: guardStart = (guardStart & 0xFF00) | value; break;
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case CTRL_GUARD_END_HIGH: guardEnd = (uint16_t)(value << 8) | (guardEnd & 0x00FF); break;
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case CTRL_GUARD_END_LOW: guardEnd = (guardEnd & 0xFF00) | value; break;
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case CTRL_DATA:
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// A byte into the destination, and the address steps on so that writing a
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// run of bytes is a loop over one instruction rather than four.
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if (canWrite(destBank, destAddress)) {
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banks[destBank].memory[destAddress] = value;
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if (destBank == BANK_TABLE) {
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// Unreachable while the table is read only, and here so that it stays
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// true if that ever changes: the published bytes are a description,
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// and nothing may write through them into a real bank.
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publishBank(BANK_TABLE);
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}
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destAddress++;
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status = 0;
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}
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break;
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case CTRL_COMMAND:
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// Both leave the addresses past whatever they touched and Length as it was,
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// so asking again carries straight on from where the last one stopped.
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switch (value) {
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case COMMAND_BLIT: doBlit(); break;
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case COMMAND_FILL: doFill(); break;
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case COMMAND_REGISTER_BANK: doRegisterBank(); break;
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case COMMAND_GUARD_ON: doGuardOn(); break;
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case COMMAND_GUARD_OFF: doGuardOff(); break;
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default:
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// Refusing an unknown command is better than ignoring it, since a
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// program that asked for something is entitled to find out that it
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// did not happen.
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refuse(VECTOR_BANK_FAULT);
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break;
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}
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break;
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default:
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// Status is read only.
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break;
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}
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return 0;
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}
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uint8_t controllerRead(uint8_t port) {
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switch (port) {
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case CTRL_SOURCE_BANK: return sourceBank;
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case CTRL_SOURCE_HIGH: return (uint8_t)(sourceAddress >> 8);
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case CTRL_SOURCE_LOW: return (uint8_t)(sourceAddress & 0xFF);
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case CTRL_DEST_BANK: return destBank;
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case CTRL_DEST_HIGH: return (uint8_t)(destAddress >> 8);
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case CTRL_DEST_LOW: return (uint8_t)(destAddress & 0xFF);
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case CTRL_LENGTH_HIGH: return (uint8_t)(length >> 8);
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case CTRL_LENGTH_LOW: return (uint8_t)(length & 0xFF);
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case CTRL_STATUS: return status;
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case CTRL_GUARD_BANK: return guardBank;
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case CTRL_GUARD_START_HIGH: return (uint8_t)(guardStart >> 8);
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case CTRL_GUARD_START_LOW: return (uint8_t)(guardStart & 0xFF);
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case CTRL_GUARD_END_HIGH: return (uint8_t)(guardEnd >> 8);
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case CTRL_GUARD_END_LOW: return (uint8_t)(guardEnd & 0xFF);
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case CTRL_DATA: {
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// A byte out of the source, stepping on the same way a write does.
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if (!canRead(sourceBank, sourceAddress)) {
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return 0;
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}
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uint8_t value = banks[sourceBank].memory[sourceAddress];
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sourceAddress++;
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status = 0;
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return value;
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}
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}
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return 0;
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}
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